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Oscillator phase noise is an important factor in designing radio frequency (RF) communications hardware. Phase noise directly contributes to adjacent-channel interference and an increase in bit error rate (BER). Understanding the operation of an oscillator can help with the oscillator design process. Also, the understanding of the noise processes within an oscillator can add insight to the design process, allowing an intelligent low-noise design. It will be shown that although simulation software can be helpful, the understanding of the oscillator operation is a valuable tool in the design process. Oscillator design will be discussed, and then the noise processes of the oscillator will be investigated. A new method of decomposing shot noise into in-phase and quadrature components will be discussed. The noise processes discussed for a non-saturating bipolar junction transistor (BJT) Colpitts oscillator will be extended to the case of a saturating BJT Colpitts oscillator. This new method gives insight into the design of low-noise oscillators, and provides guidelines for design of low-noise oscillators. Example oscillators will support the theory and low-noise design guidelines. It will be seen that although designing an oscillator to saturate can provide a stable output level over a wide bandwidth, the added noise production may degrade the performance of the oscillator through both a lower effective Q and restricted signal level compared to the noise. / Master of Science

Phase noise from radio frequency (RF) oscillators is one of the major limiting factors affecting communication system performance. Phase noise directly effects short-term frequency stability, Bit-Error-Rate (BER), and phase-locked loop adjacent-channel interference. RF oscillator circuits contain at least one active device, usually a transistor. The active device has noise properties which generally dominate the noise characteristic limits of an oscillator. Since all noise sources, except thermal noise, are generally proportional to average current flow through the active device, it is logical that reducing the current flow through the device will lead to lower noise levels. A theory based on the time-varying properties of oscillators proposes that narrowing the current pulse width in the active device will decrease the time that noise is present in the circuit and therefore, decrease phase noise even further. The time-domain waveforms and phase noise of an active-biased 700MHz oscillator are analyzed, showing heavy saturation and high harmonic content. Redesigns of the example oscillator in active-bias and four-resistor-bias configurations show improved phase noise and lower harmonic levels at the output. Five oscillator designs of each bias configuration, each having a different pulse width, are simulated. As predicted by the theory, the narrowest current pulse corresponds to the lowest phase noise of the simulated oscillators. / Master of Science

<p> A unique approach for the modeling of phase noise is examined in this thesis. In previous work regarding phase noise theory, the memory property of phase is virtually ignored. The thesis introduces the Discrete Recursive Procedure (DRP): a systematic approach or methodology to predict phase noise using a discrete recursive algorithm taking into account the memory property of phase. This discrete recursive algorithm is a general extension of the Linear Time Varying (LTV) model and is referred to as the NonLinear Time Varying (NLTV) model. </p> <p> Simulations are performed using the DRP method. Phase fluctuation comparisons are made between the LTV and the NLTV models for an ideal oscillator. The simulation results show that the NLTV model taking into account the memory property of phase makes more realistic phase noise predictions than the LTV model for asymmetrical Impulse Sensitivity Function (ISF) cases. Phase noise simulation results using the NLTV model are given for a modified 810-MHz CMOS cross-coupled LC oscillator design. At 90kHz offset, the simulation prediction (-89 dBc/Hz) and the measurement readings (-93 dBc/Hz) are closely matched with a difference of approximately 4 dBc/Hz while the CAD simulation prediction ( -101. 8) has a difference of 9 dBc/Hz from the measurements. In the phase noise simulation for the 62-MHz BIT Colpitts oscillator design, the NLTV model predicts a -26 dBc/decade and -19.5 dBc/decade for the flicker noise and thermal noise regions in accordance with the theoretical -30 dBc/decade and -20 dBc/decade slopes. </p> / Thesis / Master of Applied Science (MASc)

International Telemetering Conference Proceedings / October 27-30, 1997 / Riviera Hotel and Convention Center, Las Vegas, Nevada / This paper describes a kind of Microwave Digital Frequency Synthesizer used for S-band telemetry receivers. As well known many modern electronic systems employ a Frequency Synthesizer whose spectral purity is critical. The characteristics of a PLL (Phase-Locked Loop) Frequency Synthesizer, such as frequency resolution, phase noise, spurious suppression and switch time, should be compromised in our design. A heterodyne Frequency Synthesis is often considered as a good approach to solve the problem. But it is complicated in structure and circuit. A variable-reference-driven PLL Frequency Synthesizer was introduced which can give an improved trade-off among frequency resolution, phase noise, spurious suppression. In this paper the phase noise and spurious suppression characteristic of variable-reference-driven PLL Frequency Synthesizer is analyzed theoretically and compared with that of the heterodyne Frequency Synthesizer. For engineering application, a practical Microwave Digital Frequency Synthesizer used for telemetry receiver has been designed, which is characterized by simply structure, low phase noise and low spurious output. The output spectrum of experimental measurements is given.

International Telemetering Conference Proceedings / October 22-25, 2001 / Riviera Hotel and Convention Center, Las Vegas, Nevada / Today’s telemetry specifications are requiring electronic systems to not only survive, but operate through severe dynamic environments. Pyrotechnic shock and Random Vibration are among these environments and have proven to be a challenge for systems that rely on highly stable, low phase noise signal sources. This paper will mathematically analyze how Pyrotechnic shock and Random Vibration events deteriorate the phase noise of crystal oscillators (XO).

In today’s modern society, we are surrounded by a multitude of digital devices.The number of available digital devices is set to grow even more. As the trendcontinues, product life-cycle is a major issue in mass production of these devices.Testing and verification is responsible for a significant percentage of the productioncost of digital devices. Time efficient procedures for testing and characterization aretherefore sought for. Moreover, the need for flexible and low-cost solutions in thedesign architecture of radio frequency devices coupled with the demand for highdata rate has presented a challenge caused by interferences from the analog circuitparts. Study of digital signal processing based techniques which would alleviate theeffects of the analog impairments is therefore a pertinent subject. In the first part of this thesis, we address parameter estimation based on wave-form fitting. We look at the sinewave model for parameter estimation which iseventually used to characterize the performance of a device. The underlying goal isto formulate and analyze a set of new parameter estimators which provide a moreaccurate estimate than well known estimators. Specifically, we study the maximum-likelihood (ML) SNR estimator employing the three-parameter sine fit and derivealternative estimator based on its statistical distribution. We show that the meansquare error (MSE) of the alternative estimators is lower than the MSE of the MLestimator for a small sample size and a few of the new estimators are very close tothe Cramér-Rao lower bound (CRB). Simply put, the number of acquired measure-ment samples translate to measurement time, implying that the fewer the numberof samples required for a given accuracy, the faster the test would be. We alsostudy a sub-sampling approach for frequency estimation problem in a dual channelsinewave model with common frequency. Coprime subsampling technique is usedwhere the signals from both channels are uniformly subsampled with coprime pairof sparse samplers. Such subsampling technique is especially beneficial to lower thesampling frequency required in applications with high bandwidth requirement. TheCRB based on the co-prime subsampled data set is derived and numerical illus-trations are given showing the relation between the cost in performance based onthe mean squared error and the employed coprime factors for a given measurementtime. In the second part of the thesis, we deal with the problem of phase-noise (PHN).First, we look at a scheme in orthogonal frequency-division multiplexing (OFDM)system where pilot subcarriers are employed for joint PHN compensation, channelestimation and symbol detection. We investigate a method where the PHN statis-tics is approximated by a finite number of vectors and design a PHN codebook. Amethod of selecting the element in the codebook that is closest to the current PHNrealization with the corresponding channel estimate is discussed. We present simula-tion results showing improved performance compared to state-of-the art techniques.We also look at a sequential Monte-Carlo based method for combined channel im-pulse response and PHN tracking employing known OFDM symbols. Such techniqueallows time domain compensation of PHN such that simultaneous cancellation ofthe common phase error and reduction of the inter-carrier interference occurs. / <p>QC 20150529</p>

Au cours des dernières décennies, l’industrie de la micro-électronique a connu une large démocratisation de l’utilisation des applications de télécommunication. L’amélioration des procédés de conception et de fabrication ont permis de produire des circuits analogiques, mixtes et radiofréquences complexes et hautes performances pour ces applications. Toutefois, le coût de test de ces circuits intégrés représente encore une large part du coût de fabrication. En effet, très souvent, tester des fonctions analogiques ne se résume pas à un test fonctionnel mais signifie mesurer les spécifications du circuit. Ces mesures nécessitent l’utilisation d’instruments dédiés bien plus couteux que les ressources numériques disponibles sur un équipement de test industriel standard. Une des spécifications essentielle mais couteuse à caractériser pour les circuits RF est le niveau de bruit de phase. La technique actuellement utilisée en industrie consiste à capturer le signal à l’aide d’un canal testeur analogique équipé d’un convertisseur analogique-numérique hautes performances ; une transformée de Fourier est alors appliquée sur le signal numérisé et le bruit de phase est mesuré sur le spectre résultant. L’approche proposée dans cette thèse consiste à réaliser la mesure de bruit de phase en n’utilisant que des ressources digitales faible coût. L’idée fondamentale consiste à réaliser la capture 1-bit du signal analogique avec un canal numérique standard et à développer des algorithmes de post-traitement dédiés permettant de retrouver l’information relative au bruit de phase à partir d’une évaluation des temps de passages à zéro du signal. Deux méthodes sont présentées. La première méthode est basée sur une estimation de la fréquence instantanée du signal et une analyse de la dispersion induite par le bruit de phase. Cette méthode impose une contrainte forte quant à la fréquence d’échantillonnage à utiliser et s’est révélée sensible au bruit d’amplitude, limitant la gamme de mesures possibles. Une seconde méthode est alors proposée afin de s’affranchir de ces limitations. A partir de la capture binaire du signal analogique, une reconstruction de la phase instantanée du signal est réalisée, puis filtrée puis caractérisée grâce à un outil usuel d’évaluation de stabilité fréquentielle : la variance d’Allan. Cette technique, robuste au bruit d’amplitude et au jitter, peut être paramétrée et permet une caractérisation efficace du bruit de phase sans contrainte fondamentale. En plus des simulations, ces techniques font l‘objet d’une étude stochastique et sont validées expérimentalement sur différents types de signaux à mesurer – générés artificiellement ou provenant de puces sur le marché – et avec différentes conditions mesures – sur oscilloscope ou sur testeur industriel, en laboratoire et en production –. Une implémentation sur puce est aussi proposée et validée avec un prototype sur FPGA. / In recent decades, the microelectronics industry has experienced a wide democratization of the use of telecommunication applications. The improved process design and manufacturing have produced complex and high performance analog, mixed and radio frequency circuits for these applications. However, the test cost of these integrated circuits still represents a large part of the manufacturing cost. Indeed, very often, analog testing is not just a functional test but needs measurements for specification validations. These measurements require the use of dedicated instruments expensive resources on standard industrial test equipment.One of the essential but costly specifications to validate in RF circuitry is the phase noise level. The currently used industrial technique consists in capturing the signal from the circuit under test using an RF tester channel equipped with a high performance analog to digital converter; a Fourier transform is then applied to the digitized signal and the phase noise is measured on the resulting spectrum.The approach proposed in this thesis is to achieve the phase noise measurement using solely digital low-cost resources. The basic idea is to perform 1-bit capture of the analog signal with a standard digital channel and develop post-processing algorithms dedicated for phase noise evaluation from the zero-crossings of the signal.Two methods are presented. The first method is based on an estimate of the instantaneous signal frequency and an analysis of their dispersion induced by phase noise. This method imposes a strong constraint on the sampling frequency to be used and proved to be sensitive to noise amplitude, limiting the range of possible measures. A second method is then proposed to overcome these limitations. From the binary capture of the analog signal, a reconstruction of the instantaneous phase of the signal is carried out, then filtered and characterized by a common tool of frequency stability assessment: the Allan variance. This technique, robust to amplitude noise and jitter, can be parametrized and enables efficient characterization of phase noise without fundamental constraint.In addition to the simulations, these techniques are subject to a stochastic study and are validated experimentally on different types of signals to be measured - artificially generated or from chips on the market - and with different measuring instruments - on oscilloscope or industrial tester, in laboratory and on a production line-. An On-chip implementation is also proposed and validated with a FPGA prototype.

Modern communication systems require high performance radio frequency (RF) and microwave circuits and devices. This is becoming increasingly challenging to realize in the content of cost/size constraints. Integrated circuits (ICs) satisfy the cost/size requirement, but performance is often sacri¯ced. For instance, high quality factor (Q factor) passive components are difficult to achieve in standard silicon-based IC processes.<p>In recent years, microelectromechanical systems (MEMS) devices have been receiving increasing attention as a possible replacement for various on-chip passive elements, offering potential improvement in performance while maintaining high levels of integration. Variable capacitors (varactor) are common elements used in various applications. One of the MEMS variable capacitors that has been recently developed is built using deep X-ray lithography (as part of the LIGA process). This type of capacitor exhibits high quality factor at microwave frequencies.<p>The complementary metal oxide semiconductor (CMOS) technology dominates the silicon IC process. CMOS becomes increasingly popular for RF applications due to its advantages in level of integration, cost and power consumption. This research demonstrates a CMOS voltage-controlled oscillator (VCO) design which is used to investigate methods, advantages and problems in integrating LIGA-MEMS devices to CMOS RF circuits, and to evaluate the performance of the LIGA-MEMS variable capacitor in comparison with the conventional on-chip CMOS varactor. The VCO was designed and fabricated using TSMC 0.18 micron CMOS technology. The core of the VCO, including transistors, resistors, and on-chip inductors was designed to connect to either an on-chip CMOS varactor or an off-chip LIGA-MEMS capacitor to oscillate between 2.6 GHz and 2.7 GHz. Oscillator phase noise analysis is used to compare the performance between the two capacitors. The fabricated VCO occupied an area of 1 mm^2.<p>This initial attempt at VCO fabrication did not produce a functional VCO, so the performance of the capacitors with the fabricated VCO could not be tested. However, the simulation results show that with this LIGA-MEMS capacitor, a 6.4 dB of phase noise improvement at 300 kHz offset from the carrier is possible in a CMOS-based VCO design.