Thesis (Ph.D.)--University of Missouri-Columbia, 2006. / The entire dissertation/thesis text is included in the research.pdf file; the official abstract appears in the short.pdf file (which also appears in the research.pdf); a non-technical general description, or public abstract, appears in the public.pdf file. Title from title screen of research.pdf file viewed on (April 26, 2007). Vita. Includes bibliographical references.

One of the major trends of development of solid oxide fuel cells is to reduce the operating temperature from the high temperature range (>950°C) and intermediate temperature range (750-850°C) to the low temperature range (450-650°C). Development of low temperature oxygen ion conducting electrolytes is focused on single-phase materials including Bi2O3 and CeO2-based oxides. These materials have high ion conductivity at the low temperature range, but they are unstable in reducing environments and they are also electronic conductors. In the present research, three types of multiphase materials, Ce0.887Y0.113O1.9435 (CYO)-ZrO2, CYO- yttria-stabilized zirconia (YSZ), and CuO-CYO were investigated. We found that the conductivity of multiphase electrolyte CuO-CYO with a mass ratio of 1:3 is at least 4 times greater than that of CYO and 10 times greater than that of YSZ, the most commonly used material, obtained in the present experiments at 600°C. The enhancement of conductivity in multiphase materials correlates with the level of mismatch between the two phases. Large mismatches in terms of valance and structure result in high vacancy density and hence high oxygen ion conductivity at grain boundaries. This study demonstrates that synthesis of multiphase ceramic materials is a feasible new avenue for development of oxygen ion electrolyte material for low temperature SOFCs.

The Energy Policy Act of 1992 mandated that bathroom plumbing fixtures manufactured in the United States after January 1, 1994 meet standards for maximum water consumption. Manufacturers have developed low-consumption valves to meet these standards. The performance of low-consumption fixtures has become an important issue for facilities managers because the water saving by retrofitting low-consumption fixtures is significant. The fixtures in the Langford Architecture Building A, Texas A&M University were used to conduct this study. An acoustic information retrieval system was utilized to collect the sound signals of each fixture and a speech recognition system was utilized to identify which fixture was in use. The data from this study were analyzed to determine whether location of fixture and type of fixture—manual or automatic—caused a significant difference in frequency of use.

Copper interconnects and low k dielectrics have been introduced in advanced IC technology to reduce the interconnect resistance, improve the resistance to electromigration and reduce RC delay and cross talk effects. The introduction of new materials in integrated circuits makes the root cause determination and correction action implementation more challenging. Moreover, the complexity of package structure generates additional impact on degrading the yield of assembly processing manufacture. This main purpose of this study is to investigate the influence of introducing Cu-/Low K wafer phase on actual manufacturing situation. Issues related to the failures of assembly process were analyzed for determining the root cause, in which such as die chipping issue during die sawing process, bond pad peeling/crater issues during wire bonding process and die crack / delamination issues after pre-condition and reliability test. The DOE/JMP methodology was used to achieve the optimium assembly processing condition so as to improve the quality of products, and then the mass production with stable yield could be realized.

Field-Programmable Gate Arrays (FPGAs) are one of the most popular platforms for implementing digital circuits. Their main advantages include the ability to be (re)programmed in the field, a shorter time-to-market, and lower non-recurring engineering costs. This programmability, however, is afforded through a significant amount of additional circuitry, which makes FPGAs significantly slower and less power-efficient compared to Application Specific Integrated Circuits (ASICs). This thesis investigates three aspects of low-power FPGA design: switching activity estimation, switching activity minimization, and low-power FPGA clock network design. In our investigation of switching activity estimation, we compare new and existing techniques to determine which are most appropriate in the context of FPGAs. Specifically, we compare how each technique affects the accuracy of FPGA power models and the ability of power-aware CAD tools to minimize power. We then present a new publicly available activity estimation tool called ACE-2.0 that incorporates the most appropriate techniques. Using activities estimated byACE-2.0, power estimates and power savings were both within 1% of results obtained using simulated activities. Moreover, the new tool was 69 and 7.2 times faster than circuit simulation for combinational and sequential circuits, respectively. In our investigation of switching activity minimization, we propose a technique for reducing power in FPGAs by minimizing unnecessary transitions called glitches. The technique involves adding programmable delay elements at inputs of the logic elements of the FPGA to align the arrival times, thereby preventing new glitches from being generated. On average, the proposed technique eliminates 87% of the glitching, which reduces overall FPGA power by17%. The added circuitry increases the overall FPGA area by 6% and critical-path delay by less than 1%. Finally, in our investigation of low-power FPGA clock networks, we examine the tradeoff between the power consumption of FPGA clock networks and the cost of the constraints they impose on FPGA CAD tools. Specifically, we present a parameterized framework for describing FPGA clock networks, we describe new clock-aware placement techniques, and we perform an empirical study to examine how the clock network parameters affect the overall power consumption of FPGAs. The results show that the techniques used to produce a legal placement can have a significant influence on power and delay. On average, circuits placed using the most effective techniques dissipate 9.9% less energy and were 2.4% faster than circuits placed using the least effective techniques. Moreover, the results show that the architecture of the clock network is also important. On average, FPGAs with an efficient clock network were up to12.5% more energy efficient and 7.2% faster than other FPGAs.

This thesis consists of two distinct components: (1) Spin-polarized electron transport through aluminum array nanoparticles, (2) A single electric relaxation process in Barium Strontium Titanate (BST) nanoparticles. In the first chapter, we summarize our main results and new finding, and we also present our motivation. For the first component (chapters 2-5), we studied electron spin transport in nanometer scale aluminum grains as embedded in a ferromagnet tunneling junction. We observed tunnelling-magnetoresistance (TMR) and spin valve effects. From the TMR strong asymmetry with bias voltage, we explored spin relaxation effects. Additionally we also obtained the spin-coherence time on the order of nanoseconds by using the Hanle effect. For the second component (chapters 6-9), we investigated the dielectric response of BST and Barium Titanate (BTA) (high dielectric constant ferroelectrics) nanoparticles. The results were found to be quite unusual when compared with the dielectric response of film or bulk. The dielectric response is Debye relaxation with only a single relaxation time, and the relaxation time exhibits the Arrhenius Law at temperatures below 200 Kelvin.

This thesis presents a low-power LDPC decoder design based on speculative scheduling of energy necessary to decode dynamically varying data frame in both block-fading channels and general AWGN channels. A model of a memory-efficient low-power high-throughput multi-rate array LDPC decoder as well as its FPGA implementa- tion results is first presented. Then, I propose a decoding scheme that provides the feature of constant-time decoding and thus facilitates real-time applications where guaranteed data rate is required. It pre-analyzes each received data frame to estimate the maximum number of necessary iterations for frame convergence. The results are then used to dynamically adjust decoder frequency and switch between multiple-voltage levels; thereby energy use is minimized. This is in contrast to the conventional fixed-iteration decoding schemes that operate at a fixed voltage level regardless of the quality of data received. Analysis shows that the proposed decoding scheme is widely applicable for both two-phase message-passing (TPMP) decoding algorithm and turbo decoding message passing (TDMP) decoding algorithm in block fading channels, and it is independent of the specific LDPC decoder architecture. A decoder architecture utilizing our recently published multi-rate decoding architecture for general AWGN channels is also presented. The result of this thesis is a decoder design scheme that provides a judicious trade-off between power consumption and coding gain.

Since the early 1960s, South Korea has been going through a rapid fertility decline, along with its socioeconomic development and effective family planning programs. After achieving a desired replacement level of fertility in 1984, the total fertility rate (TFR) of Korea has gradually declined to the level of lowest-low fertility. According to 2004 vital statistics, the TFR for Korea was 1.16-below the lowest-low fertility level of 1.3. Also, Korea's fertility rates have fluctuated and varied spatially, even at the level of low fertility. Undoubtedly, Korean family planning programs have been effective in population control through the last 40 years, but since 2000, the shift to pro-natal policies indicates that Korea's fertility transition is no longer a response to family planning policies. Rather, the level of socioeconomic development is still considered to have a significant effect on Korea's fertility decline. Thus, in this thesis, the primary objective is to examine the socioeconomic determinants of fertility differentials and the variation in low fertility among the counties in South Korea in 2004. Using data from the 2000 census and 2004 vital statistics, I tested the hypothesized relationships between the level of socioeconomic development and fertility based on the demographic transition theory (DTT), by estimating several Ordinary Least Square (OLS) multiple regression models. Specifically, socioeconomic predictors, such as agricultural attainment, labor force participation, and educational attainment, were primarily examined to test the validity of the DTT hypotheses. In addition, this thesis also examined the effects of women's status and traditional norms and cultural values on variation in fertility. My results showed that the DTT is applicable to an accounting of the variance in fertility rates among the Korean counties in 2004. Although the levels of fertility are extremely low all across the country, it is apparent that socioeconomic conditions are having an impact on fertility differentials in Korea.

This thesis includes two topics. The first topic is a high speed phase adjustable ROM-less DDFS (Direct Digital Frequency Synthesizer). The second one is a low-power SRAM design. The high speed phase adjustable ROM-less DDFS employs trigonometric quadruple angle formula with the adjustability of phase and frequency. Neither any scaling tables nor error correction tables are required. In order to meet demands of general communication systems, the ROM-less DDFS is aimed at generating the frequencies for IQ channels. A pipelining design is adopted in our design to boost the frequency of the DDFS. The low-power SRAM uses a negative word-line scheme to reduce the leakage current of word-line controlled transistors (WCT). The leakage current increases with the high density of SRAM which might cause reading and writing errors. The negative word-line scheme not only reduces the leakage current as well as the power, but also makes the SRAM operate reliably during read and write cycles.

A low voltage and low power switch mode power amplifier is proposed. It is designed using TSMC 0.35£gm 2p4m CMOS process technology. It can be applied to hearing aids, and the supply voltage is 1.5V. Experimental results show that the proposed amplifier has the total harmonic distortion (THD) of 0.094% and power efficiency around 79.6%. The proposed power amplifier has superior performance in THD and power efficiency, and it is suitable for low-power low-voltage applications.