The editor's thesis, Gothenburg. / Reprinted from Göteborgs Högskolas Årsskrift, 19 and 23. eContent provider-neutral record in process. Description based on print version record.

Thesis (M. Hous. M.)--University of Hong Kong, 2001. / Includes bibliographical references.

Thesis (Ph. D.) -- University of Maryland, College Park, 2006. / Includes bibliographical references (leaves 117-119). Also available online.

The goal of this research was to study the effect of salinity on the waterflood of initially oil-wet clay-rich sand packs. Two one-foot long sand packs with 8% initial water saturation and 50% porosity were aged in crude oil for two weeks and flooded with either a low salinity (1000 ppm NaCl, pH 6.3) or a high salinity (20000 ppm CaCl, 20000 ppm MgCl, 20000 ppm NaCl, 20000 PPM KCl, pH 6.2) brine. 1D low salinity floods yield an incremental oil recovery of 15% and a significant change in the relative permeability. Initial breakthrough brine analysis showed that the low salinity flood results in more cation exchange activity compared to the high salinity case. A pH change of up to 1.4 point was witnessed for the high salinity case whereas the low salinity case had a 1.1 point pH change. The pH stayed below 7 in both low salinity and high salinity cases. The relative permeability of the low salinity case indicates a more water-wet state than that of the high salinity flood. The 2D study focused on capturing the movement of the water saturation fronts in transparent 2D sand packs via digital recordings. Two-dimensional sand packs of the oil-aged clay-rich sands were constructed in plastic quarter 5-spot models. Secondary water floods were performed. Low salinity flooding yielded higher oil recovery at breakthrough than the high salinity case. There was more areal bypassing in the case of low salinity flooding. It was difficult to pack the 2D cells uniformly which affected the water floods. / text

The Ultra-low-k material is required to reduce the RC time delay in the integrated circuits. However, the integration of the porous low-k material into the on-chip interconnects was impeded by the plasma induced damage during etching and photoresist stripping processes. This dissertation aims to study the mechanism of plasma damage to porous ultra-low-k dielectrics with the objective to minimize the damage and to develop methods and processes to restore the low-k dielectric after the plasma damage. First, the plasma etching induced surface roughening was studied on blanket porous SiCOH films in the fluorocarbon based plasma. Substantial surface roughening was found in the low polymerization region, where the surface roughening process was initiated by the unevenly distribution of surface fluorocarbon polymers in the pore structure and enhanced by ion induced surface densification. With oxygen addition, the surface densification layer increased the radial diffusion rate difference between the top and the bottom of the pits, resulting in further increase of the surface roughness. The best process optimization was found at a "threshold point" where the surface polymerization level is just high enough to suppress the roughness initiation. The second part of this dissertation investigates the mechanism of the oxygen plasma damaging process. The roles of plasma constituents (i.e. ions, radicals and photons with different wavelengths) were differentiated by an on-wafer filter system. Oxygen radical was identified as the most critical and its damage effect was enhanced by photons with wavelength smaller than 185nm. The oxygen radical kinetics in the porous structure of low-k, including diffusion, reaction and recombination, was described analytically with a plasma altered layer model and then simulated with a Monte Carlo computational method, which give guidelines to minimize the damage. The analytical model of oxygen radical kinetic process is also used to investigate the oxygen plasma damage to patterned low-k structure, which is confirmed by experiments. Finally, the dielectric recovery was studied using silylation and UV broadband thermal treatment, both individually and in combination. After both vapor and supercritical CO₂ silylation, surface carbon and hydrophobicity were partially recovered. However, the recovery effect was limited to the surface. In comparison, UV treatment can effectively remove water from the bulk of the damaged film and consolidate the silanol bonds with the help of thermal activation. The combination of UV and silylation treatments is more effectively for dielectric recovery than UV or silylation alone. The "UV first" treatment provided a better recovery in sequential processes. Under the same conditions, simultaneous treatments by silylation and UV irradiation achieved better bulk and surface recovery than the sequential process. / text

The current trends of mobile battery-powered devices make area and power critical design constraints in many applications. It is important that embedded software implementations execute any given task as power efficiently as possible. These tasks often require the computation of transcendental functions (sine, cosine, exponential, logarithm, etc.). The CORDIC algorithm can be used to implement an area-efficient hardware accelerator to assist in the computation of many of these functions while reducing the total energy consumed. This report presents the design and implementation of a fixed-point CORDIC rotator. The CORDIC rotator is used to assist in the computation of IEEE-754 single-precision floating-point exponentials. Power simulation results show the CORDIC-assisted exponent computation consumes 81.42% less energy as compared with the unassisted software solution while adding less than 10% to the gate count of the original system. / text

A Thesis submitted to The University of Arizona College of Medicine - Phoenix in partial fulfillment of the requirements for the Degree of Doctor of Medicine. / Study Design. Retrospective analysis. Objective. To determine if the use of adjunctive pain medications (subcutaneous bupivacaine, dexmedetomidine infusion, and intravenous ketorolac) will reduce the need for opioids, reduce postoperative pain, and shorten length of hospital stay in patients with adolescent idiopathic scoliosis undergoing posterior spinal fusion. Methods. Retrospective review of children 10 to 18 years with adolescent idiopathic scoliosis receiving posterior spinal fusion surgery over the past 10 years at Phoenix Children’s Hospital. Physicians managed the patients’ pain postoperatively with adjunctive medications in addition to intravenous and oral opioids. Variables of interest were local anesthetic bupivacaine delivered subcutaneously via elastomeric pain pump, sedative/analgesic dexmedetomidine infused for up to 24 hours postoperatively, and the NSAID ketorolac delivered intravenously. These three medications were used either alone or in some combination determined by the physician’s clinical judgment. Primary outcomes analyzed were normalized opioid requirement after surgery, VAS pain scores, and length of stay in the hospital. Results. One hundred and ninety-six children were analyzed with no significant differences in demographics. Univariate analysis showed that all three adjunct medications improved outcomes. A multivariate regression model of the outcomes with respect to the three medication variables of interest was developed to analyze the effects of the three medications simultaneously. The regression analysis showed that subcutaneous bupivacaine significantly reduced normalized opioid requirement by 0.98 mg/kg (P = 0.001) and reduced VAS pain scores by 0.67 points (P = 0.004). Dexmedetomidine significantly reduced the average VAS pain scores in the first 24 hours by 0.62 points (P = 0.005). Ketorolac had no effect in the multiple regression analysis. Conclusion. The use of subcutaneous bupivacaine provides good analgesia with low pain scores. A reduction in opioid requirement is beneficial and may be directly related to presence of the bupivacaine pump, although this may be limited by potential treatment bias. The three adjunct medications improve our outcomes favorably and should be studied prospectively.

A "low cost fault detection system" that identifies wheel flats and defective tracks is explored here. This is achieved with the conjunction of sensors, microcontrollers and Radio Frequency (RF) transceivers. The objective of the proposed research is to identify faults plaguing railcars and to be able to clearly distinguish the faults of a railcar from the inherent faults in the track. The focus of the research though, is mainly to identify wheel flats and defective tracks. The thesis has been written with the premise that the results from the simulation software GENSYS are close to the real time data that would have been obtained from an actual railcar. Based on the results of GENSYS, a suitable algorithm is written that helps segregate a fault in a railcar from a defect in a track. The above code is implemented using hardware including microcontrollers, accelerometers, RF transceivers and a real time monitor. An enclosure houses the system completely, so that it is ready for application in a real environment. This also involves selection of suitable hardware so that there is a uniform source of power supply that reduces the cost and assists in building a robust system.

Field-Programmable Gate Arrays (FPGAs) are one of the most popular platforms for implementing digital circuits. Their main advantages include the ability to be (re)programmed in the field, a shorter time-to-market, and lower non-recurring engineering costs. This programmability, however, is afforded through a significant amount of additional circuitry, which makes FPGAs significantly slower and less power-efficient compared to Application Specific Integrated Circuits (ASICs). This thesis investigates three aspects of low-power FPGA design: switching activity estimation, switching activity minimization, and low-power FPGA clock network design. In our investigation of switching activity estimation, we compare new and existing techniques to determine which are most appropriate in the context of FPGAs. Specifically, we compare how each technique affects the accuracy of FPGA power models and the ability of power-aware CAD tools to minimize power. We then present a new publicly available activity estimation tool called ACE-2.0 that incorporates the most appropriate techniques. Using activities estimated byACE-2.0, power estimates and power savings were both within 1% of results obtained using simulated activities. Moreover, the new tool was 69 and 7.2 times faster than circuit simulation for combinational and sequential circuits, respectively. In our investigation of switching activity minimization, we propose a technique for reducing power in FPGAs by minimizing unnecessary transitions called glitches. The technique involves adding programmable delay elements at inputs of the logic elements of the FPGA to align the arrival times, thereby preventing new glitches from being generated. On average, the proposed technique eliminates 87% of the glitching, which reduces overall FPGA power by17%. The added circuitry increases the overall FPGA area by 6% and critical-path delay by less than 1%. Finally, in our investigation of low-power FPGA clock networks, we examine the tradeoff between the power consumption of FPGA clock networks and the cost of the constraints they impose on FPGA CAD tools. Specifically, we present a parameterized framework for describing FPGA clock networks, we describe new clock-aware placement techniques, and we perform an empirical study to examine how the clock network parameters affect the overall power consumption of FPGAs. The results show that the techniques used to produce a legal placement can have a significant influence on power and delay. On average, circuits placed using the most effective techniques dissipate 9.9% less energy and were 2.4% faster than circuits placed using the least effective techniques. Moreover, the results show that the architecture of the clock network is also important. On average, FPGAs with an efficient clock network were up to12.5% more energy efficient and 7.2% faster than other FPGAs.

No description available.