In this thesis, a low overhead transport protocol for Linux networking is proposed. This proposed protocol is motivated by the observation that the transport protocol for Linux requires more than a single memory copy for both the receiving and transmission of a packet, which is essentially redundant. In this thesis, we show that all but one of the memory copies can be eliminated, thus reducing the number of memory copies to one and only one, which is in general referred to as zero copy.

The digital product increases widely and vastly. We need a converter to change analog signal to digital one. However, the requirement of analog-to-digital converter is rising due to progress of DSP (Digital Signal Processor). In most ADC structure there have an important building block called the front-end sample-and-hold circuit (SHA) . I will design and implement a high speed and low power sample and hold circuit. In this thesis, the circuits are designed with UMC 90nm 1P9M CMOS process and 1.2V of supply voltage. The speed and resolution of SHA are 100Ms/s and 10bits individually. The circuit is implemented with class AB amplifier.

The 3D applications, until recently restricted to the desktops and workstations, are expanding into the mobile platforms, such as cellular phones and PDAs. Similar to the desktop, the consumers will expect high-quality 3D experience, and this is a big challenge. Handheld devices have slower processors that are less capable of computing large workloads, and the batteries have limited lifetimes, so for large and complex workload, we need an excellent power management policy for saving power. Besides, although mobile platforms have lower resolution than desktop, each pixel must still be rendered since the screen is closed to the observer¡¦s eye, or we will see some imperfections. For the reasons above, we make a point of performance optimization and power saving, and these rely on accuracy and fast workload estimation. We refer to some workload estimation methods which researchers have mentioned before, such as UW1, UW5, PID[8], Frame Structure[9], Signature Table[1], and hybrid power management policy[10].UW1 and UW5 both use the previous workload as the estimation workload. PID uses the feedback loop to correct the estimation workload. Frame Structure classifies frames into several structures, and sums the workload of each structure up as the estimation workload. Signature Table stores some 3D parameters in the table, and when a new frame comes in, the 3D parameters of this frame will compare with the table, if match, we use the workload in the table as the estimation workload. Our method is a hybrid policy of UW1 and UW5, and we will decide to use UW1 or UW5 when a new frame comes in. Finally we will compare the performance of each power management policy.

This thesis is composed of three parts. The first part is devoted to introducing the various noise sources in transistors and their equivalent noise models. Based on the equivalent noise models, the theory of noise cancellation in a low-noise amplifier is derived in detail. The second part is to perform an experiment to validate the theory of low-noise amplifier using common-gate noise cancellation technique. By adjusting the transconductance of individual transistor, the simulated and measured noise figures are compared under different noise cancellation conditions. The third part is to design a low-noise amplifier RFIC using common-source noise cancellation technique for DVB-H applications. This RFIC was implemented in a TSMC 0.18£gm process and measured to show successful noise cancellation capability in a wide frequency range.

¡iAbstract¡j After the end of 2007, the Asus Eee PC first low price computer present to the market that creates the low-priced market of laptop computers which attracts the attention from all of computer manufacturers to launch new products to vie for the market, the Netbook (low price laptop computers) become the next ¡§Red Ocean Strategy Market¡¨ to the computer manufacturers. The Topology Research Institute estimated this kinds of low cost computer will enter the maturity development this year, and may have 680 million sets inquiry in 2010 . With the introduction of low-priced Netbook, Taiwanese manufacturers can extend its advantages of manufacturing technology and product development. Also, it leads to the booming businesses of relevant vendors and the opportunities creation of MIT (Made in Taiwan) brand development in the international market. . The research is based on the analysis of literatures, and focus on further discussions on Taiwan¡¦s current manufacturers of low-priced laptop computers and their future development trend. To understand the current business environment, industry structure, competitive advantages as well as the opportunities and challenges that Taiwan¡¦s manufacturers may face, the research chooses ASUSTeK Computer Inc. as a case study to examine its core capabilities and the strategies of Eee PC which adopts by Five Forces Analysis of Michael E. Porter. Furthermore, the research evaluates the advantages and disadvantages of its competitiveness using SWOT analysis. Finally, the research comes out with some suggestions for Asus Eee PC¡¦s future competitive strategies and development directions.

Recently, multimedia applications are used widely in many embedded and portable systems, such as mobile phones, MP3 player and PDA, which require lower power consumption within high performance constraints. Therefore, power-efficient design becomes a more important objective in Very Large Scale Integration (VLSI) designs. Moreover, the multiplication unit always lies on the critical path and ultimately determines the performance and power consumption of arithmetic computing systems. To achieve high-performance and lengthen the battery lifetime, it is crucial to develop a multiplier with high-speed and low power consumption. In multimedia and digital signal processing (DSP) applications, many low-power approaches have been presented to lessen the power consumption of multipliers by eliminating spurious computations. Moreover, the multiplication operations adopted in these systems usually allow accuracy loss to output data so as to achieve more power savings. Based on these conceptions, this dissertation considers input data characteristics and the arithmetic features of multiplications in various multimedia and DSP applications and presents novel power reduction and truncation techniques to design power-efficient multipliers and high-accuracy fixed-width multipliers. In the design of array and tree multipliers, we first propose a low power pipelined truncated multiplier which dynamically deactivates non-effective circuitry based on input range. Moreover, the proposed multiplier offers a flexible tradeoff between power reduction and product precision. This reconfigurable characteristic is very useful to systems which have different requirement on output precision. Second, a low-power configurable Booth multiplier that supports several multiplication modes and eliminates the redundant computations of sign bits in multipliers as much as possible is developed. This architecture can efficaciously decrease the power consumption of systems which demand computing performance and flexibility simultaneously. Although these two kinds of low power multipliers can achieve significant power savings, the hardware complexity of error compensation circuits and error performance in terms of the mean error and mean-square error are unsuitable for many multimedia systems composed of a large amount of multiply-accumulate operations. To efficiently improve the accuracy with less hardware complexity, we propose new error compensation circuits for fixed-width tree multipliers and fixed-width modified Booth multipliers. In the design of floating-point multipliers, we propose a low power variable-latency floating-point multiplier which is compliant with IEEE 754-1985 and suitable for 3-D graphics and multimedia applications. In the architecture, the significand multiplier is first partitioned into the upper and lower parts. Next, an efficient prediction scheme for the carry bit, sticky bit, and the upper part of significand product is developed. While the correct prediction occurs, the computation of lower part of significand multiplier is shut down and therefore the floating-point multiplication can consume less power and be completed early. In the design of modular multipliers, we propose an efficient modular multiplication algorithm to devise a high performance and low power modular multiplier. The proposed algorithm adopts the quotient pipelining and superfluous-operation elimination technique to discard the data dependency and redundant computational cycles of radix-2 Montgomery¡¦s multiplication algorithm so that the operation speed, power dissipation, and energy consumption of modular multipliers can be significantly improved.

In many multimedia applications, a little error in the output results is allowable. Therefore, this thesis presents an iterative floating-point multiplier with multiple precision to reduce the energy consumption of floating-point multiplication operations. The multiplier can provide the users with three kinds of modes. The distinction among the three modes is the accepted output error and the achievable energy saving through reducing the length of mantissa in the multiplication operation. In addition, to reduce the area of multiple precision floating-point multiplier we use the iterative structure to implement the mantissa multiplier in a floating point multiplier. Moreover the C++ language is adopted to evaluate the product error between each mode and the IEEE754 single precision multiplier. When the multimedia applications request high precision, the multiple precision floating-point multiplier will iteratively execute the 4-2 compression tree three times and the product error is around 10e-5%. The second-mode with the middle accuracy will iteratively execute the 4-2 compression tree two times and the product error is around 10e-3%. The third mode with the lowest accuracy will execute the 4-2 compression tree once and the product error is around 1%, it requires less execution cycle number. When compared with the tree-stage IEEE754 single-precision multiplier, the proposed iterative floating-point multiplier can save 42.54% area. For IDCT application, it can save 37.78% energy under 1% error constraint, For YUV to RGB application, it can save 31.36% energy under 1.1% error constraint. The experimental results demonstrate that the proposed multiple precision iterative floating-point multiplier can significantly reduce the energy consumption of multimedia applications that allow a little output distortion

Thesis (Ph. D.)--University of Texas at Austin, 1999. / Vita. Includes bibliographical references (leaves 246-268). Available also in a digital version from Dissertation Abstracts.

Zugl.: Berlin, Humboldt-University, Diss., 2009.

Thesis (M.S.)--Oregon State University, 2010. / Printout. Includes bibliographical references (leaves 68-70). Also available on the World Wide Web.