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This thesis proposes a new architecture, fabricating a pair of RITD (Resonant Interband Tunnel Diode) in the upper and lower position of drain and source terminals of a conventional MOS (Metal oxide Semiconductor), this design is completed by deposition, etching and spacer sequentially, manufacture process is a little complicate due to RITD implementation, but not difficult. This MOS based device, given to a pair of RITD in the upper and lower position of drain and source terminals, its equal model is like a conventional SRAM (Static Random Access Memory) which is completed by six MOS components at least, thus given advantages, like space occupation, cost consideration, still, due to high speed switch and low power consumption of RITD, this device also meet requirement of SRAM, because of different working mechanism, this device is more simple in interconnection and operation than that of a conventional SRAM, it is another improvement. This thesis will exhibit the manufacture process of this device and its equal circuit mode and working explanation.

High-speed systems and mobile systems are the main trends of the IC developments in these years. A high-speed system must have high-speed calculation units, such as CPUs and DSPs, and high speed memories. A high speed P-latch N-drive 4-T SRAM cell using the dual threshold voltage transistors is proposed in thesis. The high-Vth transistors are used to construct data storage latches, and the low-Vth transistors are used to improve driving capability and speed. Meanwhile, a DLL-based frequency multiplier which can provide the high speed clocks in the high speed SRAMs is also proposed. Besides a current mirror, the rest of the DLL-based frequency multiplier is a purely digital logic, which in turn eliminates the noise prone problem. Modern mobile systems usually demand a fast frequency hopping and a precise modulation. We introduce a novel method utilizing the trigonometric quadruple angle formula to reduce the spurious tones of the DDFSs, which can serve as a cosine function generator for the mobile systems. The proposed DDFS has a very high resolution. The fast frequency hopping can be achieved by the DDFS and the frequency multiplier serving a local oscillator.

This thesis includes two topics. The first topic is a high speed phase adjustable ROM-less DDFS (Direct Digital Frequency Synthesizer). The second one is a low-power SRAM design. The high speed phase adjustable ROM-less DDFS employs trigonometric quadruple angle formula with the adjustability of phase and frequency. Neither any scaling tables nor error correction tables are required. In order to meet demands of general communication systems, the ROM-less DDFS is aimed at generating the frequencies for IQ channels. A pipelining design is adopted in our design to boost the frequency of the DDFS. The low-power SRAM uses a negative word-line scheme to reduce the leakage current of word-line controlled transistors (WCT). The leakage current increases with the high density of SRAM which might cause reading and writing errors. The negative word-line scheme not only reduces the leakage current as well as the power, but also makes the SRAM operate reliably during read and write cycles.

Performance and power of sense amplifiers have big implications on the speed of caches used in microprocessors as well as power consumption of IPs in low power system on chips. The speed of voltage sense amplifiers are limited by the differential voltage development time on high capacitance SRAM bit-lines. The dynamic power increases with the differential voltage that needs to be developed on the bit-lines. This report explores multiple sense amplifier techniques - in addition to the conventional voltage sense amplifier, it analyzes current sense amplifier, charge transfer sense amplifier as wells as current latched sense amplifier and compares them in speed, area and power consumption to the voltage sense amplifier. A current sense amplifier operates by sensing the bit cell current directly and shows power and area advantages. A charge transfer sense amplifier makes use of charge redistribution between the high capacitance bit-lines and low capacitance sense amplifier output nodes to provide power benefits. This report also explores the design of a six transistor SRAM bit cell. All circuits are designed and simulated on a 45nm CMOS process. / text

The aim of the thesis is to fabricate Schottky contact carbon nanotube field effect transistor (CNFET) using the dielectrophoresis (DEP) to resolve the alignment issue and show its transistor behaviour. The work presented is a combination of fabrication and simulation of CNFET. Fabrication of the device electrode had been done using the electron beam lithography to achieve a channel length of 150nm and analysis was done on an optical microscope, SEM, AFM and Raman spectroscopy. Second half of the thesis provides a solution to “bottleneck communication” between microprocessor and memory to increase the computation for applications like AI, IoT etc and 3D monolithic memories. As a solution, we propose a novel CNFET based processing in-memory architecture using a novel CNFET dual port single-ended SRAM bit cell. The combination of the CNFET and processing in-memory can be a new phase for memory and computation.

Memory is an important part of any digital processing system. On-chip SRAM can be found in various levels of the memory hierarchy in a processor and occupies a considerable area of the chip. Leakage is one of the challenges which shrinking of technology has introduced and the leakage of SRAM constitutes a substantial part of the total leakage power of the chip due to its large area and the fact that many of the cells are idle without any access. In this thesis, we introduce asymmetric SRAM cells using stacked transistors which reduce the leakage up to 26% while increasing the delay of the cell by only 1.2% while reducing the read noise margin of the cell by only 15.7%. We also investigate an asymmetric cell configuration in which increases the delay by 33% while reduces the leakage up to 30% and reducing the read noise margin by only 1.2% compared to a regular SRAM cell.

Device identification, as human identification has been, has become critical to mitigate growing security problems. In the era of ubiquitous computing, it is important to ensure universal device identities that are versatile in number of ways, for example, to enhance computer security or to enable large-scale data capture, management and analysis. For device identities, simple labeling works only if they are properly managed under a highly controlled environment. We can also impose hard-coded serial numbers into non-volatile memories but it is well known that this is expensive and vulnerable to security attacks. Hence, it is desirable to develop reliable and secure device identification methods using fingerprint-like characteristics of the electronic devices. As technology scales, process variation has become the most critical barrier to overcome for modern chip development. Ironically, there are some research works to exploit the aggressive process variation for the identification of individual devices. They find measurable physical characteristics that are unique to each integrated circuit. Among them, device identification using initial power-up values of SRAM cells, called SRAM fingerprints, has been emphasized lately in part due to the abundant availability of SRAM cells in modern microprocessors. More importantly, since the cross-coupled inverter structure of each SRAM cell amplifies even the small mismatches between two inverter nodes, it is thus very sensitive to and maximizes the effect of random process variation, making SRAM fingerprints to acquire great features as a naturally inherent device ID. Therefore, this work focuses on achieving reliable device identification using SRAM fingerprints. As of date, this dissertation shows the most comprehensive feature characterization of SRAM fingerprints based on the large datasets measured from the real devices under various environmental conditions. SRAM fingerprints in three different process technologies - IBM 32nm SOI technology, IBM 65nm bulk technology, and TSMC 90nm low-k dielectric technology - have been investigated across different temperatures or voltages. By using formal statistical tools, the required features for SRAM fingerprints necessary to be usable as device IDs - uniqueness, randomness, independence, reproducibility, etc. - have been empirically proven. As some of the previous works mentioned, there is an inherent unreliability of the initial states of SRAM cells so that there is always some chance of errors during identification process. It is observed that, under environmental variations, the instability aggravates even more. Most of the previous work, however, ignores the temperature dependence of the SRAM power-up values, which turns out to be critical against our past speculations and becomes a real challenge in realizing a reliable SRAM-based device identification. Note that temperature variation will not be negligible in many situations, for example, authentication of widely distributed sensors. We show that it is possible to achieve SRAM-based device identification system that reliably operates under a wide range of temperatures. The proposed system is composed of three major steps: enrollment, system evaluation, and matching. During the enrollment process, power-up samples of SRAM fingerprints are captured from each manufactured device and the feature information or characterization identifier (CID) is characterized to generate a representative fingerprint value associated with the product device. By collecting the samples and the CIDs, system database gets constructed before distributing devices to the field. During the matching process, we take a single sample fingerprint of a power-cycle experiment, the field identifier (FID), and perform a match against a repository of CID's of all manufactured devices. There is an additional monitoring subsystem, called system evaluation, that estimates the system accuracy with the system database. It controls the system parameters while maintaining the system accuracy requirement. This work delivers a total-package statistical framework that raises design issues of each step and provides systematic solutions to deal with these inter-related issues. We provide statistical methods to determine sample size for the enrollment of chip identities, to generate the representative fingerprint features with the limited number of test samples, and to estimate the system performance along with the proposed system parameter values and the confidence interval of the estimation. A novel matching scheme is proposed to improve the system accuracy and increase population coverage under environmental variations, especially temperature variation. Several advanced mechanisms to exploit the instability for our benefit is also discussed along with supporting state-of-the-art circuit technologies. All these pioneering theoretical frameworks have been validated by the comprehensive empirical analysis based on the real SRAM fingerprint datasets introduced earlier. This dissertation covers a wide range of multidisciplinary research areas including solid-state device physics, computer security, biometrics, statistics, and pattern matching. The main contribution here is that this work provides a comprehensive interdisciplinary framework to enable reliable SRAM fingerprinting, even if the fingerprint, depending on ambient conditions, exhibits nondeterministic behaviors. Furthermore, the interdisciplinary bases introduced in our work are expected to provide generic fundamental methodologies that apply to device fingerprints in general, not just to SRAM fingerprints. / text

Embedded SRAMs can occupy the majority of the chip area in SOCs. The increase in process variation and aging degradation due to technology scaling can severely compromise the integrity of SRAM memory cells, hence resulting in cell failures. Enough cell failures in a memory can lead to it being rejected during initial testing, and hence decrease the manufacturing yield. Or, as a result of long-term applied stress, lead to in-field system failures. Certain types of cell failures can be mitigated through improved timing control. Post-fabrication programmable timing can allow for after-the-fact calibration of timing signals on a per die basis. This allows for a SRAM's timing signals to be generated based on the characteristics specific to the individual chip, thus allowing for an increase in yield and reduction in in-field system failures. In this thesis, a delay line based SRAM timing block with digitally programmable timing signals has been implemented in a 180 nm CMOS technology. Various timing-related cell failure mechanisms including: 1). Operational Read Failures, 2). Cell Stability Failures, and 3). Power Envelope Failures are investigated. Additionally, the major contributing factors for process variation and device aging degradation are discussed in the context of SRAMs. Simulations show that programmable timing can be used to reduce cell failure rates by over 50%.

Two different topics associated with their respective applications are proposed in this thesis. The first topic is the implementation of a 6-T SRAM cell using dual threshold voltage transistors and low power quenchers. We proposed a SRAM cell with dual threshold voltage transistors. The advantages of such a design is to reduce the access time and maintain data retention at the same time. Besides, the unwanted oscillation of the output data lines caused by large currents is reduced by adding two back-to-back quenchers. The second topic is focused on the implementation of a programmable PLL-based frequency multiplier. Using the method of a phase-locked loop and a programmable divisor to implement a frequency multiplier. ¢Ï synchronous clock signal can be generated by the proposed design. It can also be used in wireless communication systems, e.g. local oscillators.