Due to the increasing demand of three-dimensional (3D) graphic applications in various consumer electronics, how to develop a low-cost 3D graphic hardware accelerator suitable for the embedded systems has become an important issue. A typical 3D graphic accelerator includes a geometry sub-system and a rendering sub-system. In this thesis a highly-efficient 3D graphic rendering intellectual property (IP) based on the tiled-based approach is proposed. An entire rendering IP consists of several modules. The main contributions of this thesis focus on the development of the setup-engine, rasterization module, and the integration of the whole modules for the rendering IP. In the design of setup engine, the thesis develops a folded arithmetic unit architecture mainly consisting of one iterative divider, three multipliers and several adders, which can finish the overall computation of the setup equations within less than 50 cycles. As for the rasterization module, this thesis develops several scan-conversion algorithms including hierarchical, fast skip, and boundary-edge test methods suitable for the tiled-based rendering process. The ordinary line drawing algorithm for the scan-line boundary search or the direct in-out test approach is not efficient for tile-based approach since the shape of triangle primitives may become irregular after tiling. Our experimental results show that the boundary-edge test can lead to the most compact design since it can transform the normal in-out test circuit for single pixel to detect two end-points of the scan-line simultaneously. In addition, the rasterization module can be divided into the scan-line and the fragment generation parts which can help the optimization and speedup of the individual part to achieve the desired overall fill-rate goal. Our simulation shows the fill-rate improvement based on this approach is around 60%. Finally, this thesis integrates all the sub-modules to the entire rendering IP core. This IP has been realized by 0.18 um technology. The total gate count is 504k. It can run up to 166 Mhz, and deliver the peak fill rate of 333M pixels/sec and 1.3G texels/sec. This IP has been highly verified, and achieves more than 95% code coverage. It has also been integrated with OPENGL ES software module, Linux operation system and geometry module, and successfully prototyped on the ARM versatile platform.

<p> A new area-based mesh simplification algorithm is described. The proposed algorithm removes the center vertex of a polygon which consists of n ≥ 3 faces and represents that polygon with n - 2 faces. A global search method is adapted that iteratively determines which vertex is to be removed using the proposed area-based distortion measurement. Although the global search method requires more computations compared to a local search method, it guarantees better quality of approximation. Various re-triangulations are also considered to improve the perceptual quality of the final approximation.</p> <p> From multiple re-triangulations, one with minimum distortion is selected to represent the original mesh. Experimental results demonstrate the performance of the proposed algorithm for data reduction while maintaining the quality of the rendered objects. The performance of multiple description decoder when not all descriptions are available depends on the decoding strategy. By approximating lost description the distortion can be reduced. When decoder reconstructs input source without having all descriptions different methods exist to approximate the lost description. We proposed two side decoding algorithms. The proposed side decoders are based on diagonal element and the probability of input source. When low bit-rate and complicated index assignment matrix are used the side decoder based on probability of input source is recommendable. To approximate the lost description we compare the performance of standard decoding method with the performance of proposed methods. A trade-off between the performance of decoder and computational complexity exists.</p> <p> An error concealment algorithm is proposed based on flow of facial expression to improve communication of animated facial data over a limited bandwidth channel with error. Facial expression flow is tracked using dominant muscles which are those with maximum change between two successive frames. By comparing the dominant muscle data with the predetermined expression information table, facial expression flow is determined. The receiver uses linear interpolation and the information on facial expression flow to interpolate the erroneous facial animation data. For objective comparison, a distortion measurement tool, which compares two 3D objects based on point-to-point difference, is introduced. Experimental results are provided to show that the proposed error concealment method improves the quality of an animated face communications.</p> / Thesis / Master of Applied Science (MASc)

For the past few years, with the rapid advance of VLSI and multimedia technology, the applications of three-dimensional (3D) graphic applications have been widely and rapidly spread into various areas, and not longer limited into specific technical areas performed by high-end workstations. In near future, the 3D graphic engine will become an indispensable part of most multimedia systems including the entertainment television sets, the personal electronic appliances etc. A general 3D graphics engine can be divided into the geometry subsystem and the raster sub- system. The main contribution of this thesis is to design an efficient fragment pipeline process. It also helps the development of the vertex processor, and the integration of geometry and raster subsystem. In the design of the per-fragment processor, since it contains vary processing stages, such as fog blending, visible test, and alpha blending. This thesis analyzes the dependence relationship between these stages to allow several stages to run in parallel to reduce the overall pipeline latency and adjust the processing order of these stages to avoid unnecessary texturing access. This thesis also proposes two memory buffer access mechanisms suitable for the tile-based 3D graphic rendering engine to reduce the overall system memory bandwidth. The first method is to include some additional control flags for each tile such that the frequent buffer clear operations can be integrated with the normal rendering processes to avoid the additional memory clear access. The second approach is to identify the non-modified pixels in each tile by building the dirty table to reduce the number of updated pixels. The experimental results show that the proposed methods can cause more than 50% reduction of memory access. The proposed design has been realized using 0.18um technology. The gate count of the vertex processor without special functions and per-fragment processor is 201k and 118k, respectively.

In modern life, 3D graphics system is widely applied to portable product like Notebook, PDA and smart phone. Unlike desktop system, the capacity of batteries of these embedded systems is finite. Furthermore, rapid improvement of IC process leads to quick growth in the transistor count of a chip. According to above-mentioned reason and the complex computation of 3D graphics system, the power consumption will be very large. To efficiently lengthen the lifetime of battery, power management is an indispensable technique. Dynamic voltage and frequency scaling (DVFS) is one of the popular power management policy. In the scheme of DVFS, an accurate workload predictor is needed to predict the workload of every frame. According to these predictions a specific voltage and frequency level is applied to each frame of the 3D graphics system. The number of the voltage/frequency levels and the voltage/frequency of each level are fixed, the voltage/frequency table is decided according to the application of power management. Whenever the workload predictor completes the workload prediction of next frame, the voltage/frequency level of next frame will be found by looking up the voltage/frequency table. In this thesis, we propose a power management scheme with a framework composed of mainly Kalman filter and an auxiliary fuzzy controller to predict the workload of next frame. This scheme amends the shortcomings of traditional Kalman filter that needs to know the system features beforehand. And we propose a brand new concept named ¡¨delayed display¡¨ to massively reduce the miss rate of prediction without changing the framework of predictor.

Nowadays the designs of HW/SW are extremely complex. HW/SW co-verification is really difficult, consequently the new design layer, Electronic-System Level (ESL), is proposed to replace the original design flow. Today¡¦s ESL can verify the whole system simulation include the Processor, Bus, Memory¡K such as the HWs. It also can run a small program on the system. But it is hard to verify the larger program - such as the operation system because the limitations of the simulation speed. Currently some people proposed the QEMU-SystemC virtual platform. It can greatly speed up the CPU simulation speed. But the abstract simulated CPU has no timing information. It is infeasible to explore the system execution time and performance. We proposed the method: CPU, Cache, TLB and SDRAM with timing model; connect the CPU and the designed HW in TLM bus module in the HW/SW co-simulation. We can analyze the performance in the estimated timing information, and it will not take many simulation times. In addition, we developed the analysis program to show the execution time in each program block. It can help designer to locate the performance bottleneck quickly in the complex HW/SW. A case study is the 3D graphic SoC. We find the performance bottleneck in HW/SW design according the performance information purposed by our work.

Darbe yra apžvelgiamos NURBS paviršių atvaizdavimo realizavimo problemos mobiliesiems įrenginiams. Pagrindinis darbo tikslas yra įsitikinti tokios realizacijos galimumu, bei surasti kiek įmanoma efektyvesnį būdą, išsprendžiantį mobiliųjų platformų realizacijų problemas. Dar vienas tikslas, sukurti prototipinį sprendimą, padengiantį NURBS standartą. Analizei pasirinkta M3G mobiliosios grafikos standartas, kuris šiuo metu yra labiausiai paplitęs. Realizacijų palyginimui buvo pasirinkti du algoritmai: Oslo ir tiesioginis. Atlikus veikimo analizę nustatyta, jog tiesioginis algoritmas yra efektyvesnis, kurio pagrindu buvo išbaigtas NURBS standartas, realizuojant Trimmed NURBS modelius. / In the thesis it is analyzed the problems related with NURBS rendering implementation for mobile devices. The main goal of the thesis is to make find out if such implementation is possible at all and to find most effective way to implement it. One more goal is to create a prototype implementation for NURBS standard including Trimmed NURBS. M3G mobile graphics platform was chosen for analysis, which is mostly adopted across the vendors nowadays. There was chosen two rendering algorithms for analysis purposes: Oslo and directional. During analysis it was discovered, that Directional algorithm is more effective than Oslo, and it was adapted to prototype solution – Trimmed NURBS.

This thesis deals with implementation of a debugging and development tool for GLSL shader programming. In the text, you will find design of the application and it's implementation in Qt library. The thesis also includes performance testing with GLSL shaders. Experiments were focused on commands of application control flow in GLSL and texturing commands used in shaders. In the thesis, you will find explanation of the functionality of some shaders used in OpenGL. Application developed in this thesis, is meant to help with implementation of graphic programs programmed in OpenGL 3.3 or higher.

The main aim of the thesis is the reconstruction of three-dimensional surface from a~set of two-dimensional images. For the implementation of this application the programming language Java and its extension, that allows work with three-dimensional models, were chosen. First, viewing of three-dimensional models of two different file formats was necessary to allow. To create the three-dimensional models, the Marching Cubes algorithm was used. This algorithm is decribed theoretically in the text, description of the implementation and correction of deficiencies follows. Finally, the implementation of the inversion procedure of reconstruction of the three-dimensional surface, which is the extraction of two-dimensional images from the three-dimensional model, is described.

This diploma thesis deals with the creation of interactive tools for 3D computer graphics. The introduction of the thesis focuses on general theory of curves and surfaces and its mathematical description. The topics of Geometric transformation, Perspective projection and Parametric description of 3-dimensional surface are analysed in more detail. The successive chapter deals with the subject of visualisation of spatial objects in Java platform interface. The practical part describes the implementation of individual applets. JAVA programming language, which uses the library functions JOGL, was employed for the very realization of the interactive tools. The goal of the diploma thesis is the creation of a set of interactive applets in the field of computer graphics. These applets will be placed on the website of the faculty and they will serve students of VUT in Brno to improve the quality of education.

The goal of this work is to create an application, which will combine procedural and keyfram animations with subsequent visualization. Composition of this two different animations techniques is used to animate a virtual character. To combine this two techniques one starts with interpolations from keyframe animation and then enchance them by procedural animations to properly fit into the characters surroundings. This procedural part of animation is obtained by using forward and inverse kinematics. Whole application is written in C++, uses GLM math library for computations and OpenGL and GLUT for final visualization.