In order to improve the performance of simulation and the convenience of use with OSCI TLM-2.0 Standard on QEMU and SystemC based virtual platform we proposed previously called QSC, this thesis presents a novel approach for integrating OSCI TLM-2.0 with QSC. By moving the OSCI TLM-2.0 interconnect bus outside of the Bus Function Model (BFM), the proposed approach can not only accelerate the simulation speed but also make it easy to add OSCI TLM-2.0 based Intellectual Properties (IPs) to the QSC. Experimental results show that the proposed approach can speed up all the simulations by a factor from 2.8 up to 3.255 on average when compared with the previous approach.

The topic of the diploma thesis is " Application of simulation model of access network". The aim of the thesis was to create a part of the access network in which were tested simulations for TCP and UDP traffic. The theoretical part of the thesis deals with general information about the GNS3 program and the possibilities which this program allows. The next part of the thesis describes the Mikrotik RouterOS program, which was used in the topology. The next section describes the types of routing in IP networks, as well as the types of packet delivery. The practical part deals with the creation of test topologies and verification of the performance of the simulation tool. Furthermore, the practical part deals with the programming of a network generator for TCP and UDP traffic in the network. The generator was created by using a Bash script and a combination of the dd and nc commands. At the end, the thesis describes the results of simulations in terms of transmission speed, network throughput, packet size distribution and in the case of TCP also bidirectional delay – RTT.

Simulation is an essential tool for computer systems research. The speed of the simulator has a first-order effect on what experiments can be run. The recent shift in the industry to multi-core processors has put even more pressure on simulation performance, especially since most simulators are single-threaded. In this thesis, we present QEMU-MP, a parallelized version of a fast functional simulator called QEMU. / text

Virtualization is often used as a tool for resource consolidation in the server market. Virtualization is also used to simplify management tasks and provide high availability. However, the ultimate high availability feature, fault-tolerance, has been limited to special and costly hardware and software. This thesis will give an overview of how one can use virtualization tech- nologies to build a fault tolerant system, and show what would be the cost, in the sense of performance degradation when compared to a non-fault-tolerant system. 1

QEMU is a machine emulator that is able to emulate environment of various hardware platforms, including PC, PowerPC, ARM and SPARC. The goal of this master thesis is to port QEMU to HelenOS, thus allowing developers run the emulation of HelenOS inside HelenOS. The thesis contains a detailed analysis of the possible porting approaches (including the port of prerequisite libraries or their replacements) and an analysis of the features of QEMU (a reasonable subset of all features of QEMU) that are essential for achieving the goal and features that can be omitted in the prototype implementation. The primary focus of the implementation is to support the PC (x86 and x86-64) guest environment. Although not part of the prototype implementation, the thesis also focuses on analyzing the requirements for running QEMU as a virtualization hypervisor in HelenOS. Powered by TCPDF (www.tcpdf.org)

Les réseaux de capteurs sans fil sont un domaine en plein essor qui montre un potentiel intéressant pour de nombreuses applications. Pour qu’ils soient plus facilement adoptés par les industriels, il est nécessaire de démontrer que leur fonctionnement est fiable, et par conséquent de valider les protocoles utilisés par ces nœuds pour communiquer. Différentes méthodes de validation peuvent être utilisées, mais nous montrons qu’à ce jour, aucune de ces méthodes ne s’est avérée être idéale. Nous avons donc développé un nouvel outil de validation pour ces protocoles, un environnement de simulation appelé SNOOPS, capable d’exécuter le code binaire du protocole compilé sur un modèle de la plateforme hardware du nœud. Le nœud est modélisé en alliant l’émulateur de plateformes virtuelles QEMU au langage de description hardware SystemC, qui est également utilisé pour modéliser les communications en réseau entre les nœuds. Le principal attrait de SNOOPS est de posséder un module observateur qui a pour rôle d’arrêter la simulation si une propriété du protocole a été violée, afin de pouvoir trouver l’origine de l’erreur grâce à un debugger. Les propriétés du protocole à tester sont modélisées en Light Esterel, un langage réactif synchrone, à partir des spécifications du protocole, et compilées en C pour pouvoir être insérées plus simplement dans l’observateur. Un atout supplémentaire de SNOOPS est un module permettant d’interpréter et réinjecter en simulation des trames enregistrées dans un log en format pcap provenant d’expérimentations sur des nœuds physiques. Nous avons testé sur SNOOPS le protocole OCARI développé par EDF R&D et ses partenaires industriels et académiques. / Wireless sensor networks are a thriving area that shows good potential for many applications. In order for manufacturers to adopt this technology more easily, it is necessary to demonstrate that the operation of these networks is reliable, and therefore validate the protocols used by the network nodes to communicate. Different validation methods can be used, but we show that to date, none of these methods has proved to be ideal. We have therefore developed a new validation tool for these protocols, a simulation environment called SNOOPS. This tool is able to execute the binary code of the compiled protocol on a model of the node’s hardware platform. The node is modeled by combining QEMU, a virtual platform emulator, with SystemC, a hardware description language which is used in this context to model different hardware peripherals as well as the network communications between nodes. SNOOPS’s main appeal is the observer module, whose role is to stop the simulation if a protocol property has been violated, in order to find the error that is at the origin of this violation through a debugger. The properties of the protocol under test are modeled in Light Esterel, a synchronous reactive language, based on the protocol’s specifications. They are then compiled into C to be inserted more simply in the observer. An additional advantage of SNOOPS is a module to interpret and re-inject into simulation frames recorded in a pcap (packet capture) format log, from tests with physical nodes for which the origin of bugs could not be determined. We tested with SNOOPS the OCARI protocol developed by EDF R&D and its industrial and academic partners.

Today's cloud landscape has evolved computing infrastructure into a dynamic, high utilization, service-oriented paradigm. This shift has enabled the commoditization of large-scale storage and distributed computation, allowing engineers to tackle previously untenable problems without large upfront investment. A key enabler of flexibility in the cloud is the ability to transfer running virtual machines across subnets or even datacenters using live migration. However, live migration can be a costly process, one that has the potential to interfere with other applications not involved with the migration. This work investigates storage interference through experimentation with real-world systems and well-established benchmarks. In order to address migration interference in general, a buffering technique is presented that offloads the migration's read, eliminating interference in the majority of scenarios.

Nowadays the designs of HW/SW are extremely complex. HW/SW co-verification is really difficult, consequently the new design layer, Electronic-System Level (ESL), is proposed to replace the original design flow. Today¡¦s ESL can verify the whole system simulation include the Processor, Bus, Memory¡K such as the HWs. It also can run a small program on the system. But it is hard to verify the larger program - such as the operation system because the limitations of the simulation speed. Currently some people proposed the QEMU-SystemC virtual platform. It can greatly speed up the CPU simulation speed. But the abstract simulated CPU has no timing information. It is infeasible to explore the system execution time and performance. We proposed the method: CPU, Cache, TLB and SDRAM with timing model; connect the CPU and the designed HW in TLM bus module in the HW/SW co-simulation. We can analyze the performance in the estimated timing information, and it will not take many simulation times. In addition, we developed the analysis program to show the execution time in each program block. It can help designer to locate the performance bottleneck quickly in the complex HW/SW. A case study is the 3D graphic SoC. We find the performance bottleneck in HW/SW design according the performance information purposed by our work.

V informatice je pojem entropie obvykle znám jako nahodný proud dat.  Tato práce krátce shrnuje metody generovaní nahodných dat a popisuje generátor náhodnych čísel, jež je obsažen v jádře operačního systému Linux.  Dále se práce zabývá určením bitové rychlosti generování nahodných dat tímto generátorem ve virtualizovaném prosředí, které poskytují různé hypervizory.  Práce popíše problémy nízkého výkonu generátory nahodných dat ve virtualním prostředí a navrhne postup pro jejich řešení.  Poté je nastíňena implementace navržených postupů, které je podrobena testům a její vysledky jsou porovnány s původním systémem. Systém pro distribuci entropie může dále vylepšit množství entropie v sytémovém jádře o několik řádu, pokud je připojen k vykonému generátoru nahodných dat.

Infrastructure as a Service and memory forensics are two subjects which have recently gained increasing amounts of attention. Combining these topics poses new challenges when performing forensic investigations. Forensics targeting virtual machines in a cloud environment is problematic since the devices are virtual, and memory forensics are a newer branch of forensics which is hard to perform and is not well documented. It is, however an area of utmost importance since virtual machines may be targets of, or participate in suspicious activity to the same extent as physical machines. Should such activity require an investigation to be conducted, some data which could be used as evidence may only be found in the primary memory. This thesis aims to further examine memory forensics in cloud environments and expand the academic field of these subjects and help cloud hosting organisations. The objective of this thesis was to study if Virtual Machine Introspection is a valid technique to acquire forensic evidence from the virtual primary memory of a virtual machine. Virtual Machine Introspection is a method of monitoring and analysing a guest via the hypervisor. In order to verify whether Virtual Machine Introspection is a valid forensic technique, the first task was to attempt extracting data from the primary memory which had been acquired using Virtual Machine Introspection. Once extracted, the integrity of the data had to be authenticated. This was done by comparing a hash sum of a file located on a guest with a hash sum of the extracted data. The experiment showed that the two hashes were an exact match. Next, the solidity of the extracted data was tested by changing the memory of a guest while acquiring the memory via Virtual Machine Introspection. This showed that the solidity is heavily compromised because memory acquisition process used was too slow. The final task was to compare Virtual Machine Introspection to acquiring the physical memory of the host. By setting up two virtual machines and examining the primary memory, data from both machines was found where as Virtual Machine Introspection only targets one machine, providing an advantage regarding privacy.