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The fields of System-On-Chip (SOC) and Embedded Systems Design have received a lot of attention in the last years. As part of an effort to increase productivity and reduce the time-to-market of new products, different approaches for Electronic System-Level Design frameworks have been proposed. These different methods promise a transparent co-design of hardware and software without having to focus on the final hardware/software split. In our work, we focused on enhancing the component database, modeling and synthesis capabilities of the System-On-Chip Environment (SCE). We investigated two different virtual platform emulators (QEMU and OVP) for integration into SCE. Based on a comparative analysis, we opted on integrating the Open Virtual Platforms (OVP) models and tested the enhanced SCE simulation, design and synthesis capabilities with a JPEG encoder application, which uses both custom hardware and software as part of the system. Our approach proves not only to provide fast functional verification support for designers (10+ times faster than cycle accurate models), but also to offer a good speed/accuracy relationship when compared against integration of cycle accurate or behavioral (host-compiled) models. / text

In recent years, developers have wanted to design more complex and advanced embedded processors. The feasibility of developed processors must be verified before the actual application. However, the process of verification always needs high costs and time. Quick Emulator (QEMU), a virtual platform emulator, can help in this situation. It can emulate different processors and hardware environments and build a unique platform according to the designers wishes. Many people have used QEMU to emulate advanced Reduced Instruction Set Computing (RISC) processors (like ARM) or the X86 architectures. Still, there is little research on RISC-V processors. Therefore, studying the QEMU to emulate the RISC-V processor is important. This thesis aims to evaluate the performance of the RISC-V processor using QEMU. Ten different benchmarks are designed, and their results are compared to reflect the performance of the RISC-V as well as the simulator. These results provide a reference when these benchmarks are run on the RISC-V processor that is on the actual hardware development board. / De senaste åren har utvecklarna alltid velat utveckla mer komplexa och avancerade funktioner på inbyggda utvecklingskort. Men de nya funktionerna måste verifieras innan man gör kretskortet. Å andra sidan så kostar verifieringsprocessen mycket tid och pengar. Quick Emulator (QEMU), en virtuell plattformsemulator, kan hjälpa till för att lösa detta problem. Den kan emulera olika processorer och hårdvarumiljöer och bygga en unik plattform allt enligt designernas önskemål. Många människor har använt QEMU för att emulera avancerade Reduced Instruction Set Computing (RISC)-processorer (som ARM), eller X86-arkitekturerna, men det finns mycket lite forskning om RISC-V processorer. Därför är det viktigt att studera QEMU för att emulera RISC-V-processorn. Denna avhandling syftar till att utvärdera prestandan för RISC-V processorer genom att använder QEMU. Tio olika benchmarks konstrueras för att användas för att spegla prestandan hos processorn såväl som simulatorn. Dessa resultat kan sedan användas som referens när benchmarken körs på de RISC-V-processorer som finns på det aktuella hårdvaruutvecklingskortet.

Accurate virtual platforms allow for crucial, early, and inexpensive assessments about the viability and hardware constraints of software/hardware applications. The growth of multicore architectures in both number of cores and relevance in the industry, in turn, demands the emergence of faster and more efficient virtual platforms to make the benefits of single core simulation and emulation available to their multicore successors whilst maintaining accuracy, development costs, time, and efficiency at acceptable levels. The goal of this thesis is to find optimal virtual platforms to perform hardware design space exploration for multi-core architectures running filtering functions, particularly, a discrete signal filtering Matlab algorithm used for oil surveying applications running on an ARM Cortex-A53 quadcore CPU. In addition to the filtering algorithm, the PARSEC benchmark suite was also used to test platform compliance under workloads with diverse characteristics. Upon reviewing multiple virtual platforms, the gem5 simulator and the QEMU emulator were chosen to be tested due to their ubiquitousness, prominence and flexibility. A Raspberry Pi Model B was used as reference to measure how closely these tools can model a commonly used embedded platform. The results show that each of the virtual platforms is best suited for different scenarios. The QEMU emulator with KVM support yielded the best performance, albeit requiring access to a host with the same architecture as the target, and not guaranteeing timing accuracy. The most accurate setup was the gem5 simulator using a simplified cache system and an Out-of-Order detailed ARM CPU model.

Selecting the correct inter-process communication method isan important aspect of ensuring effective inter-vm and inter-container process communication. We will conduct a study ofIPC methods which might be useful and fits the Qemu/KVMvirtual machine and Docker container environments, and se-lect those that fit our criteria. After implementing our chosenmethods we will benchmark them in a test suite to find theones with highest performance in terms of speed. Our resultsshow that, at the most common message sizes, Unix DomainSockets work best for containers and Transparent Inter Pro-cess Communication has the best performance between vir-tual machines out of the chosen methods.

Existuje veľa rôznych dôvodov pre spoločnosti a organizácie, prečo by mali investovať do virtualizácie. Asi najväčší dôvod je finančná motivácia, pretože nasadenie virtualizácie môže ušetriť nemálo peňazí. Táto práca sa zaoberá práve problémom virtualizácie I/O operácií v sieťovom prostredí. Cieľom práce je tvorba softvérových ovládačov pre I/O virtualizáciu, ktoré by mohli pracovať s hardvérovo akcelerovanými sieťovými kartami. Hlavným prínosom ovládačov by mala byť použiteľnosť a čo najmenšia strata prenosového výkonu vo virtualizovanom prostredí. Pred popisom finálnych detailov ovládačov je však potrebné uviesť potrebné teoretické základy. Teoretická časť sa zaoberá súčasnými trendami vo virtualizácii I/O, technológiami ako sú virtio, vhost, SR-IOV, VFIO a mdev. V praktickej časti sú navrhuté dva spôsoby riešenia problému. Prvým je použitie technológie virtio (emulácia softvéru). Druhé je založené na technológii VFIO-mdev (hybridná paravirtualizácia). Pokiaľ sa jedná o výkon a konfigurovateľnosť zariadení, oba prístupy majú rôzne benefity. Tieto riešenia majú aj svoje nevýhody, ako je zložitosť riešenia a náročnosť integrácie do systému. Požadované ciele boli úspešne dosiahnuté vo forme prototypu ovládača nfb_mdev.