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Zuverlässigkeit 3D-integrierter Chips: Die Rolle metallischer Oberflächen und Grenzflächen / Reliability of 3D-integrated chips: The role of metallic surfaces and interfacesZschech, Ehrenfried 27 March 2013 (has links) (PDF)
Abstract des Vortrages:
The reliability-limiting effects in 3D IC structures using TSVs including mechanical stress distributions and the resulting effects on material integrity (e.g. failure modes like interface delamination, cohesive cracking, metallurgical degradation at joints, and chip-package interaction) and finally on device performance degradation are challenges in advanced 3D integration technologies and product development. Managing internal mechanical stress is a key task to ensure high reliability of products manufactured in advanced CMOS technology nodes, and it is a highly ranked concern for 3D TSV technologies. It requires the determination of materials properties, including Young’s modulus, Poisson ratio and coefficient of thermal expansion (CTE), for each material used. For polycrystalline materials, their microstructure has to be considered.
In this talk, one reliability-limiting effect, interface delamination and so-called “pop-up” of copper TSV structures will be addressed. Shear stress along the Cu/Si interface and adhesion of the interfaces in a complex stack (Si/liner/barrier/seed/Cu) are parameters that have to be considered. Metal barrier and seed films and the respective surfaces will be discussed in the context of interface strength. Nano X-ray tomography is currently the only analytical technique to study the so-called “pop-up” effect quantitatively, without modifying the region of interest.
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Zuverlässigkeit 3D-integrierter Chips: Die Rolle metallischer Oberflächen und Grenzflächen / Reliability of 3D-integrated chips: The role of metallic surfaces and interfacesZschech, Ehrenfried 27 March 2013 (has links)
Abstract des Vortrages:
The reliability-limiting effects in 3D IC structures using TSVs including mechanical stress distributions and the resulting effects on material integrity (e.g. failure modes like interface delamination, cohesive cracking, metallurgical degradation at joints, and chip-package interaction) and finally on device performance degradation are challenges in advanced 3D integration technologies and product development. Managing internal mechanical stress is a key task to ensure high reliability of products manufactured in advanced CMOS technology nodes, and it is a highly ranked concern for 3D TSV technologies. It requires the determination of materials properties, including Young’s modulus, Poisson ratio and coefficient of thermal expansion (CTE), for each material used. For polycrystalline materials, their microstructure has to be considered.
In this talk, one reliability-limiting effect, interface delamination and so-called “pop-up” of copper TSV structures will be addressed. Shear stress along the Cu/Si interface and adhesion of the interfaces in a complex stack (Si/liner/barrier/seed/Cu) are parameters that have to be considered. Metal barrier and seed films and the respective surfaces will be discussed in the context of interface strength. Nano X-ray tomography is currently the only analytical technique to study the so-called “pop-up” effect quantitatively, without modifying the region of interest.
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