Increasing complexity of Application Specific Integrated Circuits (ASICs) has demanded a corresponding increase in the power of Computer Aided Design (CAD) tools, so that contemporary design tools can now synthesise an entire silicon architecture, given only a description of its functionality. Specialised automated synthesis techniques have now been applied to almost all parts of the architecture, but one area which remains unresolved is that of memory address generators. Previously combined with other logic synthesis techniques, less than optimal solutions were often found for generating memory address sequences, and this thesis examines address generator synthesis as an individual step in the design process, as part of an investigation into high level synthesis. The synthesis techniques developed for address generators in the AG1 and AG2 tools presented target specific architectural forms including counters, incrementors and ROM look-up tables, and the details of these are gathered within a comprehensive data structure which allows optimisation through hardware sharing to occur. At a slightly higher level, the specification of address sequences as a stage in memory synthesis is also investigated and a behavioural to register-transfer level silicon compiler, MC<SUP>2</SUP> is presented. The data path and memory architectures constructed by this tool are used to produce realistic address generation requirements whose implementations are also presented, synthesised by AG2. It is shown that both array and non-array memory can benefit from more specialised address generator synthesis over the existing, mainly logic synthesis approach.

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This thesis investigates efficient codeword search algorithms and efficient clustering algorithms for vector quantization (VQ), improved codebook design algorithms and improved codebook index assignment for noisy channels. In the investigation of codeword search algorithms, several fast approaches are proposed, such as the improved absolute error inequality criterion, improved algorithms for partial distortion search, improved algorithms for extended partial distortion search and a fast approximate search algorithm. The bound for the Minkowski metric is derived as the generalised form of the partial distortion search algorithm, hypercube approach, absolute error inequality criterion and improved absolute error inequality criterion. This bound provides a better criterion than the absolute error inequality elimination rule on the Euclidean distortion measure. For the Minkowski metric of order n, this bound contributes the elimination criterion from the L<SUB>1</SUB> metric to the L<SUB>n</SUB> metric. This bound is also extended to the bound for the quadratic metric by using methods of metric transformation. The improved absolute error inequality criterion is also extended to the generalised form of the mean-distance-ordered search algorithm for VQ image coding. Several fast clustering algorithms for vector quantization based on the LBG algorithm are presented. Genetic algorithms are applied to codebook design to derive improved codevectors. The approach of stochastic relaxation is also applied to the mutation step of the genetic algorithm to further improve the codebook design algorithm. Vector quantization is very efficient for data compression of speech and images where the binary indices of the optimally chosen codevectors are used. The effect of channel errors is to cause errors in the received indices. A parallel genetic algorithm is applied to assign the codevector indices for noisy channels so as to minimize the distortion due to bit errors. The novel property of multiple global optima and the average distortion of the memoryless binary symmetric channel for any bit error in the assignment of codebook index are also introduced.

This thesis reports an investigation into integrated interface circuits for switched capacitor sensors for application in industrial process control instrumentation networks. Three circuits are presented: an absolute capacitance to voltage converter; a capacitance ratio to frequency ratio converter; and a capacitance ratio to voltage ratio converter. Of the circuits, the first two are subject to most thorough investigation with the capacitance ratio to frequency ratio converter being of particular interest. This circuit is based upon a switched capacitor, frequency controlled, negative feedback loop which permits implementation with modest quality analogue components, such as are provided with a standardcell ASIC CMOS process. Initial investigations, accomplished with discrete component implementations of the interface circuits, reveal a significant departure in behaviour from that predicted by firstorder analysis. Switch induced chargefeedthrough is shown to be responsible for the deviation. In addition, parasitic induced jitter and frequency locking are identified as a second source of error. The three interface circuits are implemented as an integrated circuit using the European Silicon Structures (ES2) ASIC CMOS process, with a modification to permit the inclusion of fullcustom designed, chargefeedthrough compensated switches. This implementation exhibits greatly reduced chargefeedthrough, and circuit behaviour is in accordance with a modification to the firstorder analysis that includes the effects of chargefeedthrough. Importantly, no frequency locking and much reduced jitter is observed. Significantly, linear performance is obtained for the capacitance ratio to frequency ratio converter over a 20 to 1 capacitance range, with operation demonstrable down to 5pF sensor capacitance.

Ion implantation and subsequent dopant activation are two of the most important fabrication steps for VLSI and ULSI circuits. The need for on-line monitoring of those steps is imperative due to the tighter tolerances being imposed by the reduction in geometries and the increase of wafer dies and wafer diameters. Knowledge of the distribution of the implanted ions with depth, both before and after activation, is crucial in the control of device performance. The aim of this project was to develop a novel approach to obtain fast and accurate implant profiles, suitable for on-line monitoring. In the new approach, the Pattern Etch Transfer (PET) technique is used to create a number of rectangular trenches of increasing depth into silicon, by use of a single photolithography step. The trenches are first patterned into photoresist by variation of the exposure time for each trench. Reactive Ion Etching (RIE) is then used to transfer those trenches into silicon, by a simultaneous etch of photoresist and the Si substrate. Implant damage, dopant profiles and carrier profiles can then be obtained from measurements performed on the flat silicon surface at the bottom of each trench. Experiments were performed to obtain better depth resolution (75 A), minimize the induced-damage levels and achieve high accuracy and repeatability. In the PET technique measurements are performed at neighbouring trenches, therefore the resulting depth profile includes an error associated with the implant variation across the wafer. The effect of the implant profile variation across the wafer was seperately assessed by use of a second method, the two-dimensional Reactive Ion Etching technique. This method is not suitable for fast monitoring since RIE is used to successively strip thin layers of Si (75 A) across the whole wafer. Etch rate variations across the wafer were measured and minimized in order to accurately determine the depth from the initial Si surface. At each depth a two-dimensional sheet resistance mapping was obtained. Two-dimensional implant profiles across the wafer can thus be acquired and 3a limits of the carrier concentration values at each depth can be obtained. Therefore, the limiting curves that are evaluated from the two-dimensional RIE technique define the upper and lower margins for the implant profile curve obtained by the PET technique. The PET technique provides a platform for the application of most of the existing implant characterization techniques. Preliminary experiments revealed the suitability of the stripping methods for monitoring of sheet resistance, optical constants and thermal-waves with depth. Differential Hall measurements were used as the benchmark test for the assessment of carrier concentration profiles obtained by the four-point probe measurements in combination with the PET structure and the two-dimension RIE technique. Damage profiles were acquired by use of ellipsometry and thermalwaves inside the PET trenches. Secondary Ion Mass Spectroscopy and SUPREM IV simulation results were used as the benchmark for dopant profiles. Shallow implants for the source/drain junctions of the 1.2tm CMOS process and high dose BF2double implants were monitored. Theoretical predictions were used to explain the resulting dopant, damage and carrier concentration profiles. The thesis also contains a critical review of ion implantation theory, problems and the most important existing monitoring and profiling techniques.

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Both polysilicon bridge and beam resonators have been fabricated and characterised. In addition, a CMP planarisation based process has been used to demonstrate a fabrication platform for producing micromechanical resonators with submicron transducer gaps. This process requires one photolithographic step less than previously reported fabrication methods and does not suffer from transducer gap widening, which otherwise strongly affects the impedance of manufactured resonators. As part of this work, pattern dependent removal rates for polysilicon have been determined and design guidelines defined to optimise the yield of CMP fabricated resonators. FIB Pt deposition on both bridge and beam resonators has been used to demonstrate location dependent bidirectional frequency tuning (-19% to +18%). In contrast to competing technologies, such as laser trimming, FIB deposition does not cause device damage. Its advantage is that it is performed at room temperature, does not require any sample preparation and no power is consumed to maintain the trimmed frequency. Real time electrochemical Ag deposition has been demonstrated to be capable of tuning polysilicon bridge resonators. It showed a location dependent bidirectional frequency change (-10% to +10.7%) using minimal power (20nW). This was implemented using an Ag deposition scheme consisting of a solid electrolyte, an Ag anode and Al contacts, and was integrated into bridge resonators using evaporation and shadow mask techniques. The advantage of this method over FIB Pt deposition is that it can provide dynamic in-situ simultaneous tuning of many resonators on the same chip.

A brief survey of filter technologies is given and the requirement for a high frequency continuous time monolithic filtering capability is identified. The ideal transconductor is defined and is compared to the other most common forms of integrated amplifier. A distinction is drawn between 'open loop' and 'closed loop' transconductor integrators. Although closed loop integrators have several advantages, filters using open loop integrators are emphasised since they have greater potential for high frequency operation. A detailed review is given of transistor level transconductor circuits in CMOS, JFET, GaAs MESFET and bipolar technologies, proposed by other researchers. Also reviewed are the techniques that have been used for the design of transconductor filters including automatic frequency and phase tuning circuits. It is demonstrated that standard methods for active-RC and switched capacitor ladder filter design are not satisfactory when applied to transconductor ladder design, particularly for bandpass responses. An original CMOS transconductance cell is described which is well suited to applications requiring high frequency of operation and high linearity within a low power supply. The advantages of designing transconductors with folded cascade ouput stages are demonstated. Also, two enhancements to the standard folded cascade structure are proposed. The first is the addition of low impedance inputs (in addition to the normal inputs). These allow the use of unidirectional capacitive branches in filters based upon open loop integrators, and thereby increase greatly the number of ladder filter structures that can be designed. The second enhancement provides control of the phase response of the transconductor by means of a variable d.c. voltage. This may be used to compensate actively for the effects of parasitic poles. A set of algebraic methods for the design of transconductor ladder filters is presented. These represent a structured method which may be used as the basis for computer aided design tools. More importantly they provide an abstract representation of the ladder which can be used to find superior active filter circuits that are not intuitively obvious. In particular, new circuits for bandpass ladders are derived which could not be obtained using conventional methods. Applying the developments described above, a set of transconductor ladder filters and a frequency control loop have been designed and fabricated on a 1 micron CMOS process. These include 1 MHz lowpass filters, along with 400 KHz and 1 MHz bandpass filters. Detailed experimental results are given for these circuits.

Surface Acoustic Wave (SAW)-controlled oscillators possess many features which make them attractive as frequency sources in communications applications. This thesis deals with SAW oscillators, both resonator and delay stabilised, and their incorporation in communications synthesisers modules intended primarily for mobile radio applications. A review of SAW technology and the theory and design of SAW controlled oscillators together with related topics on frequency synthesis techniques is included. A SAW resonator-based personal radio-telephone module is described. This module demonstrates improved performance over existing commercial equipment. VHF and UHF multi-channel digital frequency synthesisers in which SAW delay line oscillators were successfully employed as frequency sources are also presented. Finally, a SAW based UHF Gemini synthesiser is demonstrated. This module is capable of fast switching, a feature of particular interest in frequency-hopped communications. All these modules are designed using the indirect frequency synthesis approach, in which the medium and long term stabilities of the SAW oscillators are controlled by a highly stable crystal reference.

The ever increasing need to deliver electronic products quickly to the marketplace, has fuelled the development of a wide range of design automation tools which aim to increase productivity at different stages of the design cycle. Through the application of structured design methods, shorter time-to-market on increasingly complex systems has been made possible. The ability to produce electronic systems from high-level descriptions, a technique known as <i>high-level synthesis</i>, is currently an active area of research and represents the latest development in design automation. The driving force behind this, is the quest for shorter design times and the ability to handle systems of greater complexity than is possible with present tools. This thesis reports on work carried out on the design and developoment of SAGE, a novel high-level synthesis tool which generates netlist level solutions from high-level behavioural descriptions. SAGE is unique in the flexibility it allows in the choice of architecture. This is achieved through the inclusion of the designer throughout the design process Significant features of the work reported include: - An advanced time model for the description of clocked and combinatorial component behaviour. In addition the concept of indeterminate temporal behaviour is supported. - Scheduling and allocation within a hierarchical environment along with support for using components over several levels in the design hierarchy. - A flexible design cycle incorporating support for user interaction and cycle time (clock period) management throughout the synthesis process. - A novel optimisation algorithm for use in pipeline synthesis.