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This thesis investigates a number of emerging areas in interconnect metrology with a connection on the use of electrical test structures to extract parameters such as line width, sheet resistance, and the overlay of multiple layers. To address the issue of calibrating optical overlay tools, a novel design for an overlay test structure is described for use as a reference material. It was developed to demonstrate the implementation of a technique devise in collaboration with researchers at NIST and allows the cross-correlation between measurements of overlay taken with electrical and optical techniques. The next proportion of this thesis presents a test structure to evaluate the emerging field of copper interconnects. It is designed to allow electrical measurements from all-copper features, and therefore removes the complications introduced by barrier materials. The process is then used to fabricate a test chip containing line widths form 10 to 0.55 <i>μ</i>m for the evaluation of various methods for ECD extraction. In this work, sheet resistance is extracted from three varieties of test structure designs with an investigation to support the results obtained. Following this, Kelvin-tapped bridge resistor structures are measured electrically to allow the line width to be determined. Three different approaches to analysing this parameter are examined and compared to line width values taken from SEM imaging. The final area of this work concentrates on the developing field of MEMS thick film power devices. An implementation of traditional interconnect test structures in thick copper conductive tracks is conducted to evaluate their potential for process and material characteristics. This was realised with the combination of thick film photo-resist processing and copper electroplating to fabricate the test structures. An algorithm is presented which permits values for line width to be extracted from Kelvin-tapped bridge resistors without the use of pre-determined sheet resistance values.

This thesis reports on a study into the fabrication of metal oxide silicon field effect transistors using electron beam lithography to pattern features with dimensions down to 100nm and below. The study is in an area of extensive research, with devices at these dimensions of interest for future generations of integrated circuit manufacture. The design and construction of a high resolution electron beam system is reported. The system is based on a very high resolution scanning electron microscope equipped with a thermal field emission gun. Chemically amplified resist processes, for electron beam lithography, have been characterised for silicon device fabrication and sub 100nm patterns have been demonstrated. The development of a fabrication process for silicon devices, with dimensions down to 100nm, is described. The process uses electron beam lithography for all levels of patterning and electrical measurements are reported for a range of the fabricated devices. Devices fabricated in this study are used to explore a novel width modification technique using focused ion beam milling to reduce the current drive of individual transistors. The transistors are characterised before and after modification and electrical measurements are presented which provide the basis for a new chip modification strategy.

This work investigates the interface between a video sensor and a low bandwidth radio transmitter. In the context of a low-cost low-power radio video link, it outlines a hardware minimal solution. To solve the bandwidth conflict between the low power radio links and even a modest image sequence quality, a broad range of digital coding techniques are evaluated. Aspects of the coding methods other than the compression ratios they offer and the ability to implement them using minimal hardware are considered (in particular how vulnerable they leave the coded data to corruption through transmission errors). Through software simulation, implementations of the two most promising compression techniques: color quantisation with error-diffusion and localised differential predictive coding (DPCM) are further investigated. Particular emphasis is placed on implementation of the software algorithms using architectures close to those of the simplest hardware implementations. Implementation of the localised DPCM scheme is dropped on the grounds that its lossless implementation cannot offer sufficient compression, and that a lossy implementation would be too expensive in terms of the required memory. Colour quantisation with error diffusion is further pursued in the hardware implementation of two algorithms in the form of a field-programmable gate-array (FPGA). Results from the FPGA offer subjective analysis of the algorithms output at higher frame rate and the successful implementation of the architecture demonstrates the suitability to hardware implementation. A framework that was developed to allow comprehensive subjectivity testing of image processing algorithms is described and results, although statistically insignificant, are given. In evaluating the importance of the colour quantisation with error diffusion amongst other compression and coding techniques, this work concludes that where hardware is at a premium and strict viewing requirements can be met, there are applications where it can be applied profitably, offering results comparable with much more complicated solutions.

Digital systems continue to increase in size and complexity, and the associated design process has grown lengthy and expensive. A method for partitioning these designs into smaller sub-units is required for board and integrated circuit levels of implementation. In addition, rapid checks of the functionality of a particular design will require a digital system to be partitioned into the set of programmable logic devices that form a system emulator. A merge algorithm for circuit partitioning is presented in this thesis. Results are presented illustrating the performance of a software implementation of this algorithm. These results show that successful circuit partition can be efficiently achieved. The merge algorithm is based on the simple concept that cells having the maximum number of connections should be the first to be merged. Merging starts with a predefined initial size constraint on circuit groups, and it is implemented in several stages. In each stage, the size constraint on groups is enlarged to keep the merge operation active. A free competitive merge strategy followed by a leading groups merge strategy is used to ensure a good size balance between the finally partitioned groups. A pseudo-parallel merge algorithm is presented to reduce the processing time when the design to be partitioned is large. This facilitates rapid exploration of possible partition solutions. A data parallelism approach is adopted which distributes data to a number of processors. Each processor contains the same merge algorithm program operating on a different segment of the circuit netlist. Results are presented showing that the pseudo-parallel merge algorithm reduces the time to partition a circuit while maintaining the same quality of result. The predicted performance of a fully parallel implementation of the merge algorithm is also investigated. Practical and computer generated netlist are used to investigate the performance of the experimental partitioning software system.

This thesis investigates the implementation of asynchronous circuits and asynchronous computer architectures. In the area of asynchronous circuits, it proposes the direct-mapped approach to control circuit design, originally devised by Hollaar, mapped to CMOS technology. In the area of asynchronous computer architecture, it investigates scalable, concurrent computer architectures, with the aim of solving the problems of scaling performance and utilising the increasing device count. The design and implementation of two hardware structures, Shared Register Files and <i>m</i>net (micronet) architectures is detailed, together with their incorporation into the design of an asynchonous prototype processor, the A1 chip. The Shared Register File approach provides a scalable and segmented datapath by partitioning the conventional monolithic register file into multiple register files which physically share registers. Communication and synchronisation between the shared register files takes place via the shared register. This approach can be used to implement a clustered uniprocessor or a single-chip multiprocessor system. The shared register file approach allows for the exploitation of program level concurrency, where different parts of the same program or different programs can run on the different shared register file datapaths. The design and implementation of shared register files is presented. The <i>m</i>net approach is a methodology for asynchronous processor design, which allows fine-grain instruction level parallelism to be exploited. It implements a processor architecture as a non-linear pipeline with inputs at every pipeline stage. In this way, a <i>m</i>net architecture exploits more fine-grain parallelism than a conventional pipelined architecture. The design and implementation of generic, scalable <i>m</i>net architecture is described and evaluated.

No description available.

Electromigration continues to be one of the important failure mechanisms limiting the attainment of higher levels of reliability in sub-micron geometry VLSI circuits. Successful management of electromigration in future requires adoption of effective statistical process control techniques, in addition to the traditional quality control tests and inspections. The aim of this project was to develop a test structure and test methodology to monitor electromigration for metallisation process control. Based on analysis and some preliminary measurements on chequerboards, a new test structure and methodology was proposed to monitor electromigration. 'Chequerboards' are dense patterns of clear and opaque squares of metal film over silicon. As part of this study, an electromigration test chip was designed. It consists of two designs: The design EU9101 mainly contains chequerboards while EU9102 contains conventional and other electromigration test structures for comparative assessment. The chip design, fabrication and measurement details including the instrumentation aspects are also given in the thesis. One of the key process parameters, namely, linewidth is chosen to demonstrate the sensitivity of the proposed methodology to monitor electromigration. Possible applications of the new structure in electromigration measurements, other than process monitoring are also discussed. The thesis also contains a review of the electromigration measurement techniques, some measurements using the conventional test structure and a detailed discussion on the limits of conventional tests.

This thesis addresses the characterisation of these advanced photomasks. There are many techniques published that produce advanced masks, but this work deals with two of the primary ones, advanced binary masks and alternating phase shift masks (altPSM). The work covered studies the methods of extracting the three dimensional structure of these masks and uses simulation to show what effect this has upon the waves propagating through them. The thesis deals with the way in which mask inspection systems image masks and the differences inherent between the way they observe defects and the way that these defects are reproduced when printed on IC patterns. This is a vitally important component of manufacturing as the inspection tool must be calibrated to replicate a much more complex and expensive exposure tool. It is shown through simulation that smaller defects at the centre of a space rather than at the edge result in the limits of CD tolerance being reached and that the most sensitive position for a defect is not at the edge or centre of the space but rather at a position between these two. With imaging close to the theoretic limits, there is a non linear transfer of dimensional errors to the wafer. This makes it vitally important that the actual dimension on the photomask is known and on target. However the dimensions on these masks are below those normally imaged by conventional optical dimension measurement systems. The alternative used on wafers, that of scanning electron microscopy (SEM) is not reliable on masks as they have a conducting surface on an insulator. This very structure does however make them suitable for measurement with novel electrical structures. The thesis explores the potential of this technique and compares its accuracy to that of conventional optical and SEM systems showing a 99% correlation.

In radar applications, system performance depends strongly on the dynamic performance of its power supply. The operation of the transmitter causes a step-current to be drawn from its power supply, leading to a transient voltage drop. The voltage must settle to within pre-specified limits, before the arrival of the echoed pulse signals from the target, to ensure the correct functionality of the radar receiver; otherwise, some of these pulses have to be rejected. Rejected pulses reduce the accuracy of the information of the target, causing system performance to deteriorate. It is therefore vital that radar power supplies have a very robust dynamic performance to load changes. Although the transient requirements of a radar power supply are stringently specified, the precise timing of the load application is known in advance, allowing advance compensation to be made. The anticipated effect of the connection of load can be alleviated by increasing the pulse width of the converter before the load is applied, by the injection of a small voltage into the control loop. With a suitable injected voltage, significant improvement in transient response is achieved. Based on this principle, Voltage Injection Control (VIC) is proposed and investigated in this thesis. In this thesis, the implementation and design considerations of VIC are described. Time-domain optimisation using HSPICE is proposed to select a suitable injected voltage to meet the specified transient performance. Both experimental and simulated are presented, demonstrating the robustness of the technique. Utilisation of this technique in distributed power systems for future phased-array radar systems and in other possible applications is also discussed. During the course of this research, HSPICE optimisation has been applied effectively to design the control loop error amplifier compensation circuit in the time-domain, overcoming some of the limitations of the traditional frequency-domain approach.