The first part of the study focused on the preparation and assessment of healthy and viable cell cultures of primary rat cortical neurons for the study of network behaviour. Cultures were grown on silicon surfaces of varying composition and roughness to test the feasibility of integrating these cultures on silicon-based electronic devices. Also, the health and viability of neurons growing on non-transparent silicon substrates have been assessed by detailed histological analysis and cell counting using standard immunofluorescence techniques. Neurons extracted from various ganglia of the pond snail <i>Lymnaea stagnalis </i>have been prepared for patch-clamping using established dissection, isolation and enzymatic digestion protocols. The second part of the project concentrated on formulating a theory of gigaseal formation during patch-clamping by a critical review of the literature. The critical factors for highly resistive seal formation were identified and realised on prototype devices, including the patch aperture length and physical nature of the aperture surface. The physical natures of SiO₂ and Si₃N₄ (and modifications by boron deposition) were investigated by wettability experimentation. A relationship between interactive molecular surface energy and the wetting angle was obtained from an established theoretical wetting model. The third part of this study focused on the geometric properties of microfabricated apertures. Apertures were modified by deposition techniques to increase the radius of curvature of the edge profile, thereby mimicking a rounded glass pipette opening. An image analysis algorithm was developed to quantify the radius of curvature of the cross-section profile from atomic force microscopy (AFM) data. A second algorithm was developed to quantify the circularity error of the aperture top-view by analysis of the profile texture. The profile was exacted after the application of contrast enhancement and edge-detection filters from scanning electron microscopy (SEM) image data. Lastly, patch-clamp electrodes have been successfully integrated into planar silicon-based devices. This work presents the first patch-clamp microstructure capable of being scaled to a 100-μm inter-nodal spacing for construction of MEA designs.

The recent dramatic increase in research activity in the study of artificial neural networks has resulted in nonlinear systems that are capable of tasks such as classification, optimisation and content addressable memory. These successes, together with the desire to understand and mimic biological neural systems, have led to interest in the implementation of neural networks in both analogue and digital VLSI. This thesis describes the pulse stream methodology for signalling, arithmetic and communication in VLSI neural networks. A review of conventional VLSI implementations of neural networks by case study highlights the significant contributions to date in the areas of digital, mixed signal and analogue neural networks. A review of pulsed VLSI implementations of neural networks highlights research activity that is most closely related to that contained within this thesis. Several pulse stream neuron and synapse circuits have been developed and implemented in VLSI to test their operation. Methods for communicating neural state information between chips have been developed and implemented. The use of automatic set up procedures for analogue VLSI circuits are seen as essential to the development of large pulse stream neural networks and have been investigated. These circuits comprise <i>The Edinburgh Pulse Stream Cell Library</i>. The experience gained in developing this cell library has resulted in the development of a large pulse stream neural network chip, EPSILON (Edinburgh's Pulse Stream Implementation of a Learning Oriented Network), which has been demonstrated solving vowel recognition using <i>real world</i> data. A recommendation for the use of pulse stream circuits for various categories of neural network based on cells presented in this thesis has been made and forms the main contribution to knowledge of this work.

The problem of silicon assembly contains several well-separated steps that can be identified. To solve the assembly problem, use can be made of the stepwise approach to assembly, which involves finding ways of performing the individual steps and then linking the steps together to realise a silicon assembler. However, experience has shown that this approach produces poor-quality results, not because of the failure of the individual steps, but rather because of the breakdown in communication between the steps. Silicon assembly is a programming problem whose results are significantly affected by how the problem is decomposed into sub-problems. Building on the experience gained from implementing a stepwise assembler a novel integrated approach to solving the assembly problem is presented, which overcomes the communication problems inherent in the stepwise approach. Experimental results obtained using an integrated assembler are comparable to or better than those produced by existing assemblers. The integrated approach is simple in concept and easy to implement, yet produces good results, and is a suitable platform for taking silicon assembly forward in the 1990's.

The Electrically Erasable Programmable ROM (EEPROM) is used in applications such as microcontrollers and mass storage media. Each of these markets is rapidly expanding. However, EEPROMs are particularly susceptible to reliability problems, since they must survive severe voltage and current stressing. This has a knock on effect, since operating speed must be reduced, to increase reliability. Motorola's implementation of the EEPROM is the Floating Gate Electron Tunnelling MOS (FETMOS), which has been adopted for study in this thesis. An analytic model has been developed for the FETMOS, which encompasses transient response, threshold window and reliability. A good correlation has been shown between modelled data and experimental results, testifying to the model's accuracy. The effect of basic design parameters upon threshold window has been characterised, thus indicating how processing variations may be used to tailor the EEPROM threshold window. Equally, the model may be used to predict the effect of sizing down a circuit - this is important as integration densities escalate. Program endurance is the most pressing reliability issue. Modelling has indicated that large improvements may be made in this by increasing the floating gate/drain overlap, with little effect on threshold window. A novel experiment has then been devised to monitor the effect of floating gate/drain overlap and doping species, upon EEPROM reliability. For this, transistor arrays with a spectrum of well defined gate/drain offsets have been produced. The results of these are consistent with the model. It has also been found that the chemistry of the dopant has only a tangential effect upon reliability.

Dynamic, runtime reconfiguration is one of the most compelling, yet elusive applications of programmable logic. The lack of an accepted design methodology and limitations of the programmable logic interface are identified as two significant factors constraining the mainstream acceptance of runtime reconfiguration and virtual circuitry(VC). This thesis presents a framework for investigating a new form of flexible programmable logic interface capable of adapting to the demands of different VC models. An abstract architecture for virtual circuitry is presented in the context of two fundamental models of VC: the sea of accelerators and the parallel harness. The abstract architecture's position within the class of Transport Triggered Architectures(TTAs) is considered and we discuss how attributes of the architecture are harnessed to facilitate a third, sequential algorithmic VC model. A novel implementation of the abstract architecture is described; the implementation of the Ultimate RISC(URISC), a minimal microarchitecture, is presented and is then evolved into the Flexible URISC(FURI), an instance of the abstract VC architecture. A design flow and associated toolset for the FURI core is presented. This includes a discussion of the merits and complications of difference strategies for circuitry loading plus the features of a multitasking runtime environment for the FURI core, the FURI executive. Starting with the description of a simple base protocol, the design space for FURI protocols is qualified. The communication characteristics of the three VC models are described and their influence on the form of FURI protocols considered. Implementations of the Data Encryption Standard(DES) are proposed, demonstrating how the FURI system supports each of the three VC models.

MOS technology is very attractive for achieving low-cost miniature cameras. It also permits the inclusion of the sensor with other control and processing functions on the same chip. However, this technique has never been developed to the point at which MOS sensor performance matches that of CCD cameras. The objective of this project has been to develop design techniques to achieve single chip video cameras, in unmodified CMOS processes, with improved performance (aimed to match the performance of CCD cameras) and enhanced functionality. In this thesis, following an overview of solid state image sensors, the fundamentals and basic sensor array structure suitable for CMOS implementation is presented. The pixel structure and sensor array, the sense amplifier, scan circuitry, and the output amplifier and buffer are described. Noise analysis is also presented with the main noise sources highlighted and compensation schemes proposed. Other useful on-chip techniques including auto-exposure control, gain control, and data conversion are then discussed. A successfully designed device, named ASIS-1011 which incorporates all these circuit techniques, is finally reported. This design shows that the aim of achieving good picture quality and incorporating sensors and control logic on one chip can be achieved.

Continuing increases in both the size and complexity of digital signal processing (DSP) systems places a considerable demand on the design engineer to develop hardware architectures capable of fulfilling the growing functional requirements expected of modern DSP devices. Automated circuit design techniques provide the design engineer with a tool to more effectively generate high performance signal processors capable of meeting demanding specifications. Evolvable hardware (EHW) is a relatively new approach to automated circuit design which utilises advances in reconfigurable hardware technology and the power of modern micro pro­cessors to generate circuits based on the principles of natural selection and evolution. This thesis investigates the suitability of software-biased and hardware oriented programmable platforms, configured via EHW, and tailored for the automated design of high performance DSP circuits. Performance criteria such as timing, area and circuit robustness are considered. A number of benchmarked DSP circuits were initially considered. It was shown that by using larger functional logic macros as building blocks EHW is more successful at generating circuit solutions than if only gate primitives are used. In addition, the circuits generated are of comparable or better performance than equivalent circuits developed using a standard digital design methodology. Results also indicated that for more complex DSP functions to be generated, EHW platforms must use larger functional blocks, constrained for a specific application. Finite Impulse Response (FIR) filters were identified as the backbone of many DSP applica­tions, and the multiplication unit was targeted as the performance critical component. A novel Programmable Arithmetic Logic Unit (PALU) was therefore developed as a functional building block suitable for automated digital filter design using EHW. The PALU replaces coefficient multiplication with a series of bit-shifts, additions and subtractions. Two distinct arrays of PALU were developed based on conventional FPGA and PLA re-configurable hardware architectures. Results show that a PLA architecture with 2 levels of hierarchical interconnect and column-based fixed tap outputs provides a platform most suited to automated filter design using the EHW technique. The PLA was also shown to be robust to faults covering up to 25% of the array when configured using EHW.

No description available.

The design of power electronic systems requires wide ranging expertise in complex and often tedious tasks, such as the design of the power circuit, selection of power semiconductor devices, design of the feedback loop, design of wound components, and design for Electromagnetic Compatibility (EMC). Many of the tasks rely heavily on the experience of the designer, and cannot be solved analytically. This makes the design iterative, time consuming, and heavily dependent on the designer's experience. At present, circuit simulation packages such as SPICE or SABER are used to test a design in software. Even with these tools, it is still necessary to build a prototype to verify the design, usually followed by several test-modify-retest cycles before a final design is reached. This process involves considerable decision making, which requires substantial expertise in all aspects of power electronics. This thesis investigates the use of expert system technology, one of many artificial intelligence techniques, to assist in the design of power electronic systems. Faster design times and a more efficient design are among the advantages that can be achieved using an expert system based design. In this study, Switched Mode Power Supplies have been chosen as a typical power electronic system. An expert system (developed using wxCLIPS) has been linked with a circuit simulator (SPICE), extensive databases and a graphical display system to provide a comprehensive design environment. The techniques used in the system cover all facets of the design: preliminary circuit design, component selection, circuit simulation, control loop design, and design for EMC. Extensive knowledge bases covering the various design rules are built into the expert system. The design methodology aims to give a near complete system design with an optimum configuration produced at minimum time and cost. The investigated techniques could readily be adapted to other power electronic applications, such as Uninterruptible Power Supplies and motor drives.

This thesis presents the results of an investigation of the robustness of the widely used Mandani-type fuzzy logic control systems under a wide variation of parameters of the controlled process. The measurements of the dynamic performance and system robustness of a control system were firstly defined from the engineering point of view, and the concepts of the robust space and the robustness index were introduced. The robustness of the FLC systems was investigated by analyzing the structure of the fuzzy rule base and membership functions of the input-output variables. Based on the close relation of the fuzzy rule base and the system dynamic trajectory on the phase plane, a switching line method is introduced to qualitatively analyze the dynamic performance of the SISO FLC systems. This switching line method enables the qualitative prediction of the shape and position of the robust space of the FLC controlled first order processes and second order processes. The effects of FLC parameters on system robustness were also investigated. The movements of the position and the shape of the switching line with the variation of the controller parameters were analyzed, and its relation with the system performance was reported. Three methods were proposed to improve the robustness of the FLC system. The first design method proposed was based on the switching line characteristics of the FLC system. The second method, called phase advanced FLC, was introduced to handle the control of high order processes with fuzzy algorithms. The third method was an evolutionary method based on the genetic algorithm which was used to automatically design a robust fuzzy control system, assuming the availability of the controlled process model.