No description available.

Bit-Serial architecture and Gallium Arsenide have essentially been mutually exclusive fields in the past. Digital Gallium Arsenide integrated circuits have increasingly adopted the conventional approach of bit-parallel structures that do not always suit the properties and problems of the technology. This thesis proposes an alternative by using a least significant bit first bit-serial architecture, and presents a group of 'cells' designed for signal processing applications. The main features of the cells include the extensive use of pseudo-dynamic latches for pipelining, modularity, and programmability. The logic circuits are mainly based on direct-coupled FET logic. They are also compatible with silicon ECL circuits. The target clock rates for these cells are 500MHz, at least ten times faster than previous silicon bit-serial circuits. The differences between GaAs and silicon technologies meant that the cells were designed from circuit level upwards. Further to these cells, a multi-level signaling scheme has been developed to substantially alleviate off-chip signaling. Synchonisation between signals are simplified, improving even further on the conventional bit-serial system, especially at the high bit-rates encountered in GaAs circuits. For on-chip signals, a single phase clock scheme has been developed for the GaAs cells, which maintains the low clock loading and high speed charactersitics of the pseudo-dynamic cells, while substantially simplifying clock distribution and generation. Two novel latch designs are proposed for this scheme. Test results available have already proved the concepts behind the two-phase clocking scheme, the latches, and the multi-level scheme. Further tests are taking place to establish their speed performance.

The contributions of this thesis are four fold. Firstly, the implementation of COST 259 directional channel model in terms of tapped delay line is developed. While the implemented channel model facilities link level simulation, capacity analysis indicates that the delay spread has relatively small impact as compared to the azimuth spread (AS) on the channel capacity. Secondly, an antenna model which incorporates various antenna effects into the performance study of antenna arrays (AAs0 is developed. A comprehensive study of these effects through computer simulations reveals that the use of ideal parameters in the literature always over-predicts the actual system performance. The use of different antenna configurations yields different results with some arrays performing better in certain scenario than others. Furthermore, a proposed mutual coupling (MC) model explains the conflicting results reported to date in the literature. The overall effect of MC is to reduce the system performance despite lower fading correlation is being obtained between the pair of elements when MC is taken into account. Thirdly, the impact of using different azimuth-of-arrival (AOA) and elevation-of-arrival (EOA) distributions on the performance of various AAs is found to be minimal. The determining factor for the AA performance is the standard deviation of the underlying distribution. Finally, three-dimensional spatial fading correlation (SFC) models for several CAA geometries are developed. The closed-form SFC functions are expressed in terms of AOA, EOA and the geometry of the AA under study. Such closed-form expressions can be used to determine the correlation matrices at both base station and mobile station and thus are important in assisting the capacity analysis of single-input multiple-output and multiple-input and multiple-output systems. Furthermore, the developed SFC functions also enable the sensitivity of the AAs to be evaluated through the performance patterns. The results provide invaluable insight that can ultimately assist the design of AA algorithms. An extensive analysis on the array’s sensitivity shows that the system performance is more AS dependent than ES while the effect of mean-azimuth-of-arrival and mean-evaluation-of-arrival is array dependent. The results also show that the AS is the primary factor affecting antenna correlation and the impact of ES is mainly noticeable at small AS values. Nevertheless, in evaluating the performance of AAs, both AOQ and EOA must be taken in account. Capacity analysis also demonstrates the practicability of deploying electromagnetic vector sensor (EVS) and EVS arrays as compact AA receivers.

The emergence of the MMIC as a cost effective, compact and enabling technology has increased the need for accurate CAD software. The performance of nonlinear MMICs must be evaluated during design using computer simulation, since they cannot be tuned after fabrication. Simulation relies upon accurate large-signal models for circuit components and this project involves the development of the GaAs MESFET large-signal model. In this work, the model is empirical and is derived entirely from characterizing S-parameter measurements over a range of bias levels and frequencies. Small-signal equivalent circuits are calculated from each set of S-parameter measurements and the nonlinear model is constructed from the complete set of equivalent circuits. Frequency dispersion in the conductances of the MESFET creates differences in the device characteristics at low and high frequencies. Extra nonlinear elements have been therefore added to the nonlinear model, to account for these effects. A series of MMIC circuits have been designed. Nonlinear measurements have been made and are compared with time domain simulations using the nonlinear model. Results indicate that this modelling approach is more accurate than one based on DC measurements, which does not account for the effects of frequency dispersion.

Advanced Lithography continues to be the limiting factor in the drive for higher levels of microcircuit integration. The key to the successful management of a lithography process is the integration of full measurement and instrumentation functions with the process, and the adoption of effective process control strategies. The aim of this research is to improve the understanding of critical dimension (CD) control by an investigation of the sources of variations in linewidth dimensions. Having identified the key factors, it should be possible to characterize and control their influence. Experimental analysis suggests that film thickness and photoresist thickness have a profound effect on linewidth dimensions. Simulation techniques are used to establish a theory which uses standing wave patterns within film stacks to predict reflectance and exposure threshold, as well as the dimensions of the developed resist images. This theory is later corroborated by measurements on test wafers. Having established the need to monitor film thickness variations, a novel metrology technique which incorporates both film thickness and linewidth uniformity measurements is introduced. The technique is based on the optical characteristics of a 'chequerboard' test pattern, consisting of clear and opaque squares. The chequerboard effectively enhances deviations in CD by translating changes in linewidth into an area change on the chequerboard. The technique was originally based on the measurement of light transmitted through glass wafers. The implementation of the technique using reflectance from silicon wafers is described, and possible future developments of the system are discussed.

The thesis first examines the use of the cross-bridge electrical linewidth structure to measure the sheet resistance and critical dimensions of copper damascene interconnect. This was achieved through computer simulation of current flow in the structures and served to highlight the effects of the damascene process on the measurement. As a result layout design rules have been defined which minimise the errors introduced by diffusion barrier layers and dishing. Mono-crystalline silicon linewidth structures are being developed to meet the requirements for traceable metrology standards. The proposed test structures are fabricated using a wet etch process and have unusual geometries which affect their operation. Computer simulation has shown that the effects of surface interface charge and substrate biasing are the key issues that need to be addressed for accurate extraction of sheet resistance. This work has identified that increased doping of the silicon starting material reduces these effects. The use of on-mask electrical linewidth structures for alternating aperture phase shifting mask metrology has been investigated. The results compare very favourably, in terms of repeatability, with those obtained using the more common CD-SEM technique. Photolithographic simulation of submicron test structure layouts has been used to investigate the effects of applying optical proximity correction to cross-bridge linewidth structures. The effects of severe asymmetries on the Greek cross sheet resistance structure have also been examined. Finally the thesis presents examples of process characterisation using resistive test structures. In the first of these examples cross-bridge linewidth structures are used to quantify the effects of a bulk silicon, wet etch solution, which was designed to passivate metal interconnect, on the dimensions of aluminium tracks. This is followed by an investigation of the use of novel sheet resistance test structures to characterise the deposition of platinum in a focused ion beam system. The platinum sheet resistance has been characterised in terms of the main process parameters which facilitates the fabrication of resistive elements of a known value.

Discrete event simulation has grown up as a practical technique for estimating the quantitative behaviour of systems, where direct measurement is undesirable or impractical. It is also used to understand the detailed behaviour of such systems. Its theory is largely that of experimental science. Theories of simulation largely centre on statistical approaches to validating the measures generated by models, rather than on the verification of their detailed behaviour. This dissertation presents an approach to understanding the correctness of the behaviour of discrete event simulation models, using Milner's Calculus of Communicating Systems (CCS). It is shown that a framework based on the process view of models can be constructed for hierarchical modelling, where both performance and functional properties are of interest. As a formal basis for this framework, a hierarchical graphical modelling language (Extended Activity Diagrams) is developed. A semantics is developed for this language, in terms of CCS. This language is shown to map onto the major constructs of the DEMOS discrete event simulation language, extended to allow hierarchical modelling and to resolve certain ambiguities. The result is a new version of DEMOS known as <I>modified</I> DEMOS. A graphically driven tool based on such a framework is presented. It allows modellers to use a combination of simulation and functional techniques to answer both performance questions (what is the throughput under a certain load) and functional questions (will the system deadlock under certain assumptions). In particular this tool can support process oriented simulations of models, using <I>modified</I> DEMOS, and functional analysis, based on both the basic version and the timed extension of Milner's Calculus of Communicating Systems and using the Concurrency Workbench. A number of examples of interesting applications of this approach to typical models are presented.

The continuing scaling of CMOS devices for performance advantages has resulted in an accompanying thinning of the gate oxide insulator and an increase in the level of hot carrier effects for a fixed power supply voltage. Nitrogen incorporated into the gate oxide through the nitridation of silicon oxide from a gas source has been extensively studied to improve the robustness of devices to hot carrier effects. Although reduced growth rates have been observed with nitrided oxides, there has not been a comprehensive study of MOS device performance utilising this mechanism to selectively grow gate oxides with different thicknesses. One of the advantages is their potentially improved hot carrier robustness through the incorporation of nitrogen. The dry oxidation kinetics of silicon implanted with low dose (10<SUP>14</SUP>-10<SUP>15</SUP> cm<SUP>-2</SUP>) molecular nitrogen has been extensively studied in this work to establish the possibility of using the implanted nitrogen for adjusting the oxidation rate of silicon. This work established that the oxidation rate is determined by the pile-up of nitrogen at the silicon oxide-silicon interface in a surface reaction rate limited process. The nitrogen implanted silicon technique has been incorporated into a 0.5μm CMOS process to determine the feasibility of growing multiple thicknesses of gate oxide during a single oxidation step. In this work, the gate oxide is grown after direct implantation of molecular nitrogen into both NMOS and PMOS device areas. This allows for easy integration into an existing process as the implantation is carried out during the same step as threshold adjustment implants. The hot carrier reliability and boron penetration properties of gate oxides grown under high nitrogen dose conditions are improved in a similar way to nitridation from a gas source. Increased nitrogen dose in the silicon however, shows a deterioration of the MOS device mobility and gate oxide integrity. The localised thinning of the gate oxide is shown to be responsible and the inhomogeneous redistribution of nitrogen is attributed to the deterioration of the device characteristics. Sufficient device performance and reliability however can be achieved using low dose molecular nitrogen such that the simultaneous growth of 150Å and 90Å gate oxides can be realised on a CMOS technology microprocessor chip for 3.3V and 5V power supply interface applications.

In integrated circuit manufacture, in particular, quality assurance, QA, is increasing rapidly in importance and in this research methods are developed and assessed which will assist with this. A review of current IC manufacturing is presented and CMOS technology shown to be dominant with BiCMOS seen to be a growth area. The role of Statistical Process Control, SPC, and the end for QA is also reviewed. This thesis addresses the problem and has defined some new techniques for the process control of a standard CMOS process. The approach is a novel one employing the concept of parasitic bipolar transistor test structures as a process control tool for present day CMOS circuits and, even more importantly, for BiCMOS devices. Test chip design and manufacture for the project are presented and the techniques proposed include: a) characterisation of parasitic JFETs to provide well depth information electrically b) the use of parasitic lateral bipolar transistors to estimate the sideways diffusion component associated with MOS transistors fabricated in a CMOS process c) the use of parasitic bipolar test structures to evaluate CMOS process uniformity. They provide useful parameters for processcontrol and, in some cases, have even been demonstrated to be more sensitive to CMOS process non-uniformities than those extracted from MOS devices themselves. Also process control information for today'sCMOS processes and an insight into the control of future BiCMOS processes.

The development of in-situ structural health monitoring (SHM) techniques represents a challenge for offshore wind turbines (OWTs) in order to reduce the cost of the operation and maintenance (O&M) of safety-critical components and systems. This thesis propos- es an in-situ wireless SHM system based on acoustic emission (AE) techniques. The proposed wireless system of AE sensor networks is not without its own challenges amongst which are requirements of high sampling rates, limitations in the communication bandwidth, memory space, and power resources. This work is part of the HEMOW- FP7 Project, ‘The Health Monitoring of Offshore Wind Farms’. The present study investigates solutions relevant to the abovementioned challenges. Two related topics have been considered: to implement a novel in-situ wireless SHM technique for wind turbine blades (WTBs); and to develop an appropriate signal pro- cessing algorithm to detect, localise, and classify different AE events. The major contri- butions of this study can be summarised as follows: 1) investigating the possibility of employing low sampling rates lower than the Nyquist rate in the data acquisition opera- tion and content-based feature (envelope and time-frequency data analysis) for data analysis; 2) proposing techniques to overcome drawbacks associated with lowering sampling rates, such as information loss and low spatial resolution; 3) showing that the time-frequency domain is an effective domain for analysing the aliased signals, and an envelope-based wavelet transform cross-correlation algorithm, developed in the course of this study, can enhance the estimation accuracy of wireless acoustic source localisa- tion; 4) investigating the implementation of a novel in-situ wireless SHM technique with field deployment on the WTB structure, and developing a constraint model and approaches for localisation of AE sources and environmental monitoring respectively. Finally, the system has been experimentally evaluated with the consideration of the lo- calisation and classification of different AE events as well as changes of environmental conditions. The study concludes that the in-situ wireless SHM platform developed in the course of this research represents a promising technique for reliable SHM for OWTBs in which solutions for major challenges, e.g., employing low sampling rates lower than the Nyquist rate in the acquisition operation and resource constraints of WSNs in terms of communication bandwidth and memory space are presented.