Genetic programming is an approach that utilises the power of evolution to allow computers to evolve programs. While loops are natural components of most programming languages and appear in every reasonably-sized application, they are rarely used in genetic programming. The work is to investigate a number of restricted looping constructs to determine whether any significant benefits can be obtained in genetic programming. Possible benefits include: Solving problems which cannot be solved without loops, evolving smaller sized solutions which can be more easily understood by human programmers and solving existing problems quicker by using fewer evaluations. In this thesis, a number of explicit restricted loop formats were formulated and tested on the Santa Fe ant problem, a modified ant problem, a sorting problem, a visit-every-square problem and a difficult object classification problem. The experimental results showed that these explicit loops can be success fully used in genetic programming. The evolutionary process can decide when, where and how to use them. Runs with these loops tended to generate smaller sized solutions in fewer evaluations. Solutions with loops were found to some problems that could not be solved without loops. The results and analysis of this thesis have established that there are significant benefits in using loops in genetic programming. Restricted loops can avoid the difficulties of evolving consistent programs and the infinite iterations problem. Researchers and other users of genetic programming should not be afraid of loops.

This paper proposes an isolation layer -- a shim -- betweeninter-domain routing and packet forwarding. The job of this layer isto coordinate between Autonomous Systems (AS's) on when and how tomodify the forwarding state to ensure inter-domain routing loops donot cause forwarding loops. The benefits of a consistency layer aretwofold. First, it prevents the creation of transient inter-domainforwarding loops and the resulting packet loss, high latency, andconnection failures.Second, by taking the burden of forwarding consistency off theinter-domain routing protocol, it enables inter-domain routingprotocols with more complex convergence characteristics than BGP, suchas protocols that optimize route selection based on performance. Weoffer two possible designs for the consistency layer. We prove thatboth designs are free of forwarding loops and show they are easy todeploy in the current Internet.

Phase locked loops (PLLs) used to generate high precision clocks are integral components in the majority of modern day electronic systems such as Analog-to-Digital Converters (ADC), Digital-to-Analog Converters (DAC), transceivers, processors, etc. The accuracy of this clocks that effects the overall performance of the system is measured in terms of its jitter, phase noise, spurious tones, etc. For example, the jitter in an ADC sampling clock can result in uncertainty of the sampling instant and can result in degradation of the effective number of bits (ENOB) of the ADC, phase noise on the other hand can result in reciprocal mixing in receivers and leakage into adjacent channels in transmitters. Therefore it is very desirable to design PLLs that generate clean clocks with minimal area and power consumption. This thesis discusses two PLL prototypes in 65nm CMOS technology. The first prototype demonstrates a sub-sampling phase detector (SSPD) based feed-forward noise cancellation (FFNC) scheme in a Type-II ring oscillator (RO) PLL. The FFNC technique uses the already available noise information at the SSPD output and cancels it from the PLL output. The proposed FFNC achieves a 1.4x reduction in jitter, 19.5dB power supply induced noise suppression at the PLL output while consuming a small area of 0.022mm2. The second prototype demonstrates a Type-I SSPD based RO PLL. The SSPD sample-and-hold action generates a steady-state voltage to tune the VCO directly. This eliminates the issue of high reference spurs generally associated with a Type-I PLL. Also the Type-I PLL occupies a very low area of 0.008mm2 as it avoids the usage of bulky integrating capacitor generally used in a Type-II PLL. The PLL with 2.4GHz output achieves a phase noise of -122.6dBc/Hz at a 1MHz offset and the power consumption is 6.1mW. It achieves reference spurs of -64.2dBc, RMSjitter of 422fs and FoMjitter of -239.7dB. In addition to the two prototypes, a theoretical discussion on an auxiliary FFNC (AFFNC) cancellation scheme that can work with a generic Type-II RO PLL is also included. The AFFNC technique uses a stand alone SSPD to extract and cancel noise from the VCO output. The SSPD is embedded into an alignment loop for proper noise extraction and cancellation. Along with AFFNC, which uses one reference edge for noise extraction, a Double Sampled AFFNC (DS-AFFNC) which utilizes both the rising and falling edge of the reference for noise extraction is also included. By using both the reference edges, higher cancellation BW is achieved.

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Thesis (M.S.)--Oregon State University, 2009. / Printout. Includes bibliographical references (leaves 43-45). Also available on the World Wide Web.

Thesis (M.S.)--Oregon State University, 2006. / Printout. Includes bibliographical references (leaves 29-30). Also available on the World Wide Web.

Thesis (M.S.)--Montana State University--Bozeman, 2005. / Typescript. Chairperson, Graduate Committee: Steven R. Shaw. Includes bibliographical references (leaf 42).

Thesis (MScIng)--University of Stellenbosch, 2008. / Bibliography. Also available via the Internet.