Increasing power consumption and heat dissipation are becoming urgent challenges for processors today and in the future. Digital power control architectures in which processors closely interact with voltage regulators are becoming necessary to enhance system energy efficiency. Digital techniques offer advantages such as flexibility, fewer external components and reduced overall cost as compared to conventional analog techniques. The primary objective of this thesis is to develop new digital control architecture for processor voltage regulators with low complexity and high dynamic performance. A digital control technique to naturally implement the desired output impedance is proposed. In this technique, Adaptive Voltage Positioning (AVP) is implemented by generating a dynamic voltage reference and a dynamic current reference to achieve the desired output impedance. A dual-voltage-loop control with dynamic reference step adjustment, non-linear control and a dedicated transient detection circuit is proposed to improve the dynamic performance. The dynamic reference step adjustment method lowers the high speed requirement of reference update clock; the non-linear control minimizes the transient-assertion-to-action delay and maximizes the inductor current slew rate; and the transient detection circuit recognizes the load transient state in a manner adaptive to the amount and slew rate of load transient. Theoretical, simulation and experimental results prove the effective operation and excellent performance of the controller. Finally, the dynamic performance of the voltage regulator with the proposed digital controller under large-step load oscillations is proven by simulation and experimental results. / Thesis (Ph.D, Electrical & Computer Engineering) -- Queen's University, 2008-07-31 13:14:52.149

The Dynamic Voltage Scaling (DVS) technique has proven to be ideal in regard to balancing performance and energy consumption of a processor since it allows for almost cubic reduction in dynamic power consumption with only a nearly linear reduction in performance. Due to its virtue, the DVS technique has been used for the two main purposes: energy-saving and temperature reduction. However, recently, a Dynamic Voltage Scaled (DVS) processor has lost its appeal as process technology advances due to the increasing Process, Voltage and Temperature (PVT) variations. In order to make a processor tolerant to the increasing uncertainties caused by such variations, processor designers have used more timing margins. Therefore, in a modern-day DVS processor, reducing voltage requires comparatively more performance degradation when compared to its predecessors. For this reason, this technique has a lot of room for improvement for the following facts. (a) From an energy-saving viewpoint, excessive margins to account for the worst-case operating conditions in a DVS processor can be exploited because they are rarely used during run-time. (b) From a temperature reduction point of view, accurate prediction of the optimal performance point in a DVS processor can increase its performance. In this dissertation, we propose four performance improvement ideas from two different uses of the DVS technique. In regard to the DVS technique for energy-saving, in this dissertation, we introduce three different types of margin reduction (or margin decision) techniques. First, we introduce a new indirect Critical Path Monitor (CPM) to make a conventional DVS processor adaptive to its given environment. Our CPM is composed of several Slope Generators, each of which generates similar voltage scaling slopes to those of potential critical paths under a process corner. Each CPR in the Slope Generator tracks the delays of potential critical paths with minimum difference at any condition in a certain voltage range. The CPRs in the same Slope Generator are connected to a multiplexer and one of them is selected according to a current voltage level. Calibration steps are done by using conventional speed-binning process with clock duty-cycle modulation. Second, we propose a new direct CPM that is based on a non-speculative pre-sampling technique. A processor that is based on this technique predicts timing errors in the actual critical paths and undertakes preventive steps in order to avoid the timing errors in the event that the timing margins fall below a critical level. Unlike direct CPM that uses circuit-level speculative operation, although the shadow latch can have timing error, the main Flip-Flop (FF) of our direct CPM never fails, guaranteeing always-correct operation of the processor. Our non-speculative CPM is more suitable for high-performance processor designs than the speculative CPM in that it does not require original design modification and has lower power overhead. Third, we introduce a novel method that determines the most accurate margin that is based on the conventional binning process. By reusing the hold-scan FFs in a processor, we reduce design complexity, minimize hardware overhead and increase error detecting accuracy. Running workloads on the processor with Stop-Go clock gating allows us to find which paths have timing errors during the speed binning steps at various, fixed temperature levels. From this timing error information, we can determine the different maximum frequencies for diverse operating conditions. This method has high degree of accuracy without having a large overhead. In regard to the DVS technique for temperature reduction, we introduce a run-time temperature monitoring scheme that predicts the optimal performance point in a DVS processor with high accuracy. In order to increase the accuracy of the optimal performance point prediction, this technique monitors the thermal stress of a processor during run-time and uses several Look-Up Tables (LUTs) for different process corners. The monitoring is performed while applying Stop-Go clock gating, and the average EN value is calculated at the end of the monitoring time. Prediction of the optimal performance point is made using the average EN value and one of the LUTs that corresponds to the process corner under which the processor was manufactured. The simulation results show that we can achieve maximum processor performance while keeping the processor temperature within threshold temperature. / text

It can be expected that digital controllers will be increasingly used in low voltage, high-current and high frequency voltage regulator modules (VRMs) where conventional analog controllers are currently preferred because of the cost and performace reasons. However, there are still remaining two significant challenges for the spread of the digital control techniques: quantization effects and the delay effects. Quantization effects might introduce the limit cycle oscillations (LCOs) to the converter, which will generate the stability issues. Actually, LCOs can not be totally eliminated theoretically. One way to reduce the possibilities of LCOs is to employ a high resolution Digital Pulse-Width-Modulator (DPWM). However, designing such a DPWM which can meet the requirements of VRMs application requires ultra-high system clock frequency, up to several GHz. Such high frequency is impractical due to huge power consumption. Hybrid DPWM might be an alternative solution but will occupy large silicon area. Single phase digital constant on-time modulation method is another good candidate to improve the DPWM resolution without adding too much cost. However, directly extending this method to multi-phase application, which is the prevalent structure in VRMs application, will introduce some issues. With more phases in parallel, the duty cycle resolution will drop more. To solove the mentioned issue, this work proposed a multi-phase digital constant on-time modulation method. The proposed method will control the control voltage to alternate between two adjacent values, or dither, within one switching period. The outcome is that the phase duty cycle's resolution is improved and independent on phase number. Compared with conventional constant frequency modulation method, the proposed method can achieve about 10 times higher duty cycle resolution for the VRM application. The effectiveness of the proposed method is verified by the simulation as well as the experiment results. Delay effect is another concern for the digital controlled VRMs. There exist several types of delays in the digital feedback loop, including the ADC conversion delay, digital compensator calculation delay, DPWM delay as well as some propagation delays. Usually these delays are inside the digital controller and it is hard to know the exact values. There are several papers talking about the small signal models of the digital voltage mode control. These models are valid only if all the delay terms are known exactly since each delay is considered separately. Actually, this process is not easy. Moreover, there is no literature talking about the complete small signal model of the digital VRMs. But in reallity, different implementations of the sampling process will give different impacts to the loop. This work proposed the small signal signal models of digital VRMs. The analysis is based on the assumptions that DPWM is a double-edge modulation and the sampling instants are aligned with the middle of one phase's off time. At first, the conversion and calculation delay is neglected. The focus of the modeling is on the small signal model of the current sampling methods and the DPWM delay. This model is valid for those digital controllers which have fast ADC and fast calculation capabilities. It is shown that even with a "fast" controller, the current sampling and DPWM might introduce some delay to the loop. After that, the conversion and calculation delay are considered into the modeling. Two time periods, T1ff and T1rr, are employed to describe the total delay effects in the control loop. It is observed that the total delay in the loop is integral times of sampling periods, which is never reported by any other literatures. Therefore, the proposed model only includes one delay term and the value of this delay can be found through a pre-determined lookup table. Finally, the complete small signal model of the digital VRMs considering the conversion and calculation delay is proposed. This model is helpful for the researchers to find the delay effects in their control loop based on the range of the total physical delay in the controller. With the derived small signal mondels of digital VRMs, the design guildeline for AVP control are presented. The digital active-droop control is employed and it borrows the concept of constant output impedance control from the analog world. Two design examples are provided for the verification. / Master of Science

Clock Distribution Networks play a vital role in performance and reliability of a system. However, temperature gradients observed in 3D ICs hamper the functionality of CDNs in terms of varying skew and propagation delay. This thesis presents two compensation techniques, Adaptive Voltage and Controllable Delay, to overcome these problems. The compensation methods are validated using a FPGA-based test vehicle. Modification in traditional buffer design are also presented and the performance as well as the area and power overhead of both the implementations is compared.