Thesis (M.App.Sc.) - Carleton University, 2007. / Includes bibliographical references (p. 143-145). Also available in electronic format on the Internet.

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Thesis (M. A.) --University of Limpopo, 2021 / This is an exploratory study conducted to assess the effectiveness of the digital migration in South Africa. This study focused on two areas of domicile, which embarked on the process of migrating in Limpopo Province i.e. Shayandima Village in Thohoyandou and Rapotokwane Village in Bela-Bela. The theories that were used to guide the study were the diffusion of innovations theory, political economic theory and media policy theory. These theories were employed to assist in assessing the process, the effectiveness and the importance of Digital Migration. The results for this study are revealed that 85% of respondents asserted that digital broadcasting is very effective and easy to use compared to the analog broadcasting systems, as it shows clear pictures, quality sound and access to more television channels. This help television viewers to get quality television programs. It was interesting to note that respondents mentioned that they did not regret migrating from analog to digital broadcasting because of the benefits and impact that the Set Top Boxes Set (STB)s have on their televisions. The findings reveal that the STBs are effective and affordable and enable to watch more television channels. There is also a need for the Department of Communication and Digital Technologies to ensure that every household in South Africa migrates to digital broadcasting system

This thesis presents a study on solutions to high-speed analog-to-digital conversion in CMOS image sensors using time-interpolation methods. Data conversion is one of the few remaining speed bottlenecks in conventional 2D imagers. At the same time, as pixel dark current continues to improve, the resolution requirements on imaging data converters impose very high system-level design challenges. The focus of the presented investigations here is to shed light on methods in Time-to-Digital Converter interpolation of single-slope ADCs. By using high-factor time-interpolation, the resolution of single-slope converters can be increased without sacrificing conversion time or power. This work emphasizes on solutions for improvement of multiphase clock interpolation schemes, following an all-digital design paradigm. Presented is a digital calibration scheme which allows a complete elimination of analog clock generation blocks, such as PLL or DLL in Flash TDC-interpolated single-slope converters. To match the multiphase clocks in time-interpolated single-slope ADCs, the latter are generated by a conventional open-loop delay line. In order to correct the process voltage and temperature drift of the delay line, a digital backend calibration has been developed. It is also executed online, in-column, and at the end of each sample conversion. The introduced concept has been tested in silicon, and has showed promising results for its introduction in practical mass-production scenarios. Methods for reference voltage generation in single-slope ADCs have also been looked at. The origins of error and noise phenomenona, which occur during both the discrete and continuous-time conversion phases in a single-slope ADC have been mathematically formalized. A method for practical measurement of noise on the ramp reference voltage has also been presented. Multiphase clock interpolation schemes are difficult for implementation when high interpolation factors are used, due to their quadratic clock phase growth with resolution. To allow high interpolation factors a time-domain binary search concept with error calibration has been introduced. Although the study being conceptual, it shows promising results for highly efficient implementations, if a solution to stable column-level unit delays can be found. The latter is listed as a matter of future investigations.

Continuous-time (CT) Delta-Sigma Modulators (DSMs) have re-gained popularity recently for oversampling analog-to-digital conversion, because they are more suitable for low supply voltage implementation than their discrete-time (DT) counterparts, among other reasons. To the state of art at the low voltage front, a CT O.5-V audio-band DSM with a return-to-open feedback digital-to-analog converter has been reported. However, the O.5-V CT DSM has a limited performance of 74-dB SNDR due to clock jitters and other factors caused by the ultralow supply. / Finally, a O.5-V 2-1 cascaded CT DSM with SCR feedback is proposed. A new synthesis method is presented. Transistor-level simulations show that a 98dB SNDR is achieved over a 25-kHz signal bandwidth with a 6.4MHz sampling frequency and 350muW power consumption under a 0.5-V supply. / In this thesis, three novel ULV audio-band CT DSMs with high signal-to-noise-plus-distortion ratio (SNDR) are reported for a nominal supply of O.5V. The first one firstly realizes a switched-capacitor-resistor (SCR) feedback at O.5V, enabled by a fast amplifier at O.5V, for reduced clock jitter-sensitivity. Fabricated in a O.13mum CMOS process using only standard VT devices, the 3rd order modulator with distributed feedback occupies an active area of O.8mm2 . It achieves a measured SNDR of 81.2dB over a 25-kHz signal bandwidth while consuming 625muW at O.5-V. The measured modulator performance is consistent across a supply voltage range from O.5V to O.8V and a temperature range from -20°C to 90°C. Measurement results and thermal-noise calculation show that the peak SNDR is limited by thermal noise. / The scaling of the feature sizes of CMOS technologies results in a continuous reduction of supply voltage (VDD) to maintain reliability and to reduce the power dissipation per unit area for increasingly denser digital integrated circuits. The VDD for low-power digital circuits is predicted to drop to O.5V in about ten years. Ultra-low voltage (ULV) operation will also be required for the analog-to-digital converter, a universal functional block in mixed-signal integrated circuits, in situations where the benefits of using a single VDD out-weigh the overhead associated with multi-V DD solutions. / The second ULV CT DSM employs a feed-forward loop topology with SCR feedback. Designed in O.13mum CMOS process, the modulator achieves a post-layout simulation (thermal noise included) result of 89dB SNDR over a 25-kHz signal bandwidth. The 0.13mum CMOS chip consumes an active area of O.85mm2 and 682.5muW at O.5-V supply. It achieves an excellent measured performance of 87.8dB SNDR over a 25-kHz signal bandwidth and al02dB spurious-free dynamic range. To the best of our knowledge, this performance is the highest for DSMs in this supply voltage range. Thanks to the proposed adaptive biasing technique, the measured modulator performance is consistent across a supply voltage range from O.4V to O.75V and a temperature range from -20°C to 90°C. / Chen, Yan. / Adviser: Kong Pang Pun. / Source: Dissertation Abstracts International, Volume: 73-04, Section: B, page: . / Thesis (Ph.D.)--Chinese University of Hong Kong, 2011. / Includes bibliographical references (leaves 127-135). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [201-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese.

Este trabalho aborda um sistema de aquisição de dados (SAD) analógico-digital, baseado em um esquema redundante com diversidade de projeto, que é testado em dois ambientes diferentes de radiação. O primeiro experimento considera um teste de dose total ionizante (Total Ioninzig Dose - TID) sob irradiação gama, e o segundo experimento considera os efeitos de eventos singulares (Single Event Effects - SEE) sob irradiação por íons pesados. O SAD é composto, principalmente, por três conversores analógicos-digitais (ADCs) e dois votadores. A técnica usada é a Redundância Modular Tripla (Triple Modular Redundancy - TMR), com implementação em diferentes níveis de diversidade (temporal e arquitetural). O sistema é construído em um System-on-Chip programável (PSoC 5LP) da Cypress Semiconductor, fabricado em tecnologia CMOS de 130nm. Para a irradiação com TID, se utiliza o PSoC de part number CY8CKIT-050 sob uma fonte de radiação gama de 60Co (cobalto-60), com uma taxa de dose efetiva de 1 krad(Si)/h por 10 dias, atingindo uma dose total de 242 krad(Si) Para SEE se utiliza o protótipo PSoC de part number CY8CKIT-059 (sem encapsulamento) em um acelerador de partículas 8UD Pelletron usando 16O (oxigeno-16) ao vácuo, com energia de 36 MeV em um LET aproximado de 5.5 MeV/mg/cm2 e uma penetração no silício de 25 mm, resultando em um fluxo de 354 p/cm2.s, e uma fluência de 5077915 p/cm2 depois de 14755 segundos (4h 09min). Observou-se com o resultado do primeiro estudo que um (1) dos módulos do sistema apresentou uma degradação significativa na sua linearidade durante a irradiação, enquanto os outros tiveram uma degradação menos grave, mantendo assim a funcionalidade e confiabilidade do sistema. Durante o tempo de irradiação do segundo estudo, foram observadas 139 falhas: 53 SEFIs (Single Events Funtional Interrupt), 29 falhas críticas e 57 falhas SDC (Silent Data Corruption), atingindo as diferentes copias do sistema e um dos votadores do mesmo, mas sempre mantendo a saída esperada. Nos dois experimentos se evidencia a vantagem de usar a diversidade de projeto, além do TMR, para melhorar a resiliência e confiabilidade em sistemas críticos redundantes que trabalham com sinais mistos. / This work presents an analog-to-digital data acquisition system (DAS) based on a redundant scheme with design diversity, being tested in two different radiation environments. The first experiment is a Total Ionizing Dose (TID) essay and the second one considers Single Event Effects (SEE) under heavy ion irradiation. The DAS is mainly composed of three analog-todigital converters (ADCs) and two voters. The used technique was the Triple Modular Redundancy (TMR) implementing different levels of diversity (temporal and architectural). The circuit was built in a programmable System-on-Chip (PSoC 5LP) from Cypress Semiconductor, fabricated in a 130nm CMOS technology process. For the irradiation with TID the part number CY8CKIT-050 PSoC was used under a 60Co (cobalt-60) gamma radiation source, with an effective dose rate of 1 krad(Si)/h during 10 days, reaching a total dose of 242 krad(Si). For SEE experiments the part number CY8CKIT-059 (without encapsulation) PSoC prototype under a 8UD Pelletron particle accelerator using 16O (oxigen-16) under vacuum, with an energy of 36 MeV, resulting in a flux of 354p/cm2.s and a fluence of 5077915p/cm2 after 14755 seconds (4h 09min). As result of the first study it was observed that one of the system’s modules presented a significant degradation in its linearity during the irradiation, while degradations in the other modules were not as deep, maintaining the system’s functionality and reliability. During the period of the radiation of the second study, 139 faults were observed, 82 of them were critical and 57 were SDC (Silent Data Corruption), reaching the different system copies and one of the voters, while always maintaining the correct output. The advantage of using diversity, besides TMR, to improve resilience and reliability in redundant systems working with mixed signals was demonstrated in both experiments.

The thesis covers a series of PC programs that we have written that will enable users to easily design FIR linear phase lowpass digital filters and multistage sampling rate conversion systems. The first program is a rewrite of the McClellanParks computer program with some slight modifications. The second program uses an algorithm proposed by Rabiner that determines the length of a lowpass digital filter. Rabiner used a formula proposed by Herrmann et al. to initially estimate the filter length in his algorithm. The formula, however, assumes unity gain. We present a modification to the formula so that the gain of the filter is normalized to accommodate filters that have a gain greater than one (as in the case of a lowpass filter used in an interpolator). We have also changed the input specifications from digital to analog. Thus, the user supplies the sampling rate, passband frequency, stopband frequency, gain, and the respective maximum band errors. The program converts the specifications to digital. Then, the program iteratively estimates the filter length and interacts with the McClellan-Parks Program to determine the actual filter length that minimizes the maximum band errors. Once the actual length is known, the filter is designed and the filter coefficients may be saved to a file. Another new finding that we present is the condition that determines when to add a lowpass filter to a multistage decimator in order to reduce the total number of filter taps required to implement the system. In a typical example, we achieved a 34% reduction in the total required number of filter taps. The third program is a new program that optimizes the design of a multistage sampling rate conversion system based upon the sum of weighted computational rates and storage requirements. It determines the optimum number of stages and the corresponding upsampling and downsampling factors of each stage of the design. It also determines the length of the required lowpass digital filters using the second program. Quantization of the filter coefficients may have a significant impact on the frequency response. Consequently, we have included a routine within our program that determines the effects of such quantization on the allowable error margins within the passband and stopband. Once the filter coefficients are calculated, they can be saved to files and used in an appropriate implementation. The only requirements of the user are the initial sampling rate, final sampling rate, passband frequency, stop band frequency, corresponding maximum errors for each band, and the weighting factors to determine the optimization factor. We also present another new program that implements a sampling rate conversion from CD (44.1 kHz) to DAT (48 kHz) for digital audio. Using the third program to design the filter coefficients, the fourth program converts an input sequence (either samples of a sine wave or a unit sample sequence) sampled at the lower rate to an output sequence sampled at the higher rate. The frequency response is then plotted and the output block may be saved to a file.

Graduation date: 1996

Advances in electronic systems have lead to the demand for high resolution, high bandwidth Analog-to-Digital Converters (ADCs). Oversampled ADCs are well- known for high accuracy applications since they benefit from noise shaping and they usually do not need highly accurate components. However, as a consequence of oversampling, they have limited signal bandwidth. The signal bandwidth (BW) of oversampled ADCs can be increased either by increasing the sampling rate or reducing the oversampling ratio (OSR). Reducing OSR is a more promising method for increasing the BW, since the sampling speed is usually limited by the technology. The advantageous properties (e.g. low in-band quantization, relaxed accuracy requirements of components) of oversampled ADCs are usually diminished at lower OSRs and preserving these properties requires complicated and power hungry architectures. In this thesis, different combinations of delta-sigma and pipelined ADCs are explored and new techniques for designing oversampled ADCs are proposed. A Hybrid Delta-Sigma/Pipelined (HDSP) ADC is presented. This ADC uses a pipelined ADC as the quantizer of a single-loop delta-sigma modulator and benefits from the aggressive quantization of the pipelined quantizer at low OSRs. A Noise-Shaped Pipelined ADC is proposed which exploits a delta-sigma modulator as the sub-ADC of a pipeline stage to reduce the sensitivity to the analog imperfection. Three prototype ADCs were fabricated in 0.18μm CMOS technology to verify the effectiveness of the proposed techniques. The performance of these architectures is among the best reported for high bandwidth oversampled ADCs. / Graduation date: 2011

In this thesis we discuss design and implementation of low-complexity digital filters. Digital filters are key components in most digital signal processing (DSP) systems and are, for example, used for interpolation and decimation. A typical application for the filters considered in this work is mobile communication systems, where high throughput and low power consumption are required. In the first part of the thesis we discuss implementation of high throughput lattice wave digital filters (LWDFs). Here arithmetic transformation of first- and second-order Richards’ allpass sections are proposed. The transformations reduces the iteration period bound of the filter realization, which can be used to increase the throughput or reduce the power consumption through power supply voltage scaling. Implementation of LWDFs using redundant, carry-save arithmetic is considered and the proposed arithmetic transformations are evaluated with respect to throughput and area requirements. In the second part of the thesis we discuss three case studies of implementations of digital filters for typical applications with requirements on high throughput and low power consumption. The first involves the design and implementation of a digital down converter (DDC) for a multiple antenna element radar receiver. The DDC is used to convert a real IF input signal into a complex baseband signal composed of an inphase and a quadrature component. The DDC includes bandpass sampling, digital I/Q demodulation, decimation, and filtering and three different DDC realizations are proposed and evaluated. The second case study is a combined interpolator and decimator filter for use in an OFDM system. The analog-to-digital converters (ADCs) and the digital-to-analog converters (DACs) work at a sample rate twice as high as the Nyquist rate. Hence, interpolation and decimation by a factor of two is required. Also, some channel shaping is performed which complicates the filter design as well as the implementation. Frequency masking techniques and novel filter structures was used for the implementation. The combined interpolator and decimator was successfully implemented using an LWDF in a 0.35 mm CMOS process using carry-save arithmetic. The third case study is the implementation of a high-speed decimation filter for a SD ADC. The decimator has an input data rate of 16 Gsample/s and the decimation factor is 128. The decimation is performed using two cascaded digital filters, a comb filter followed by a linear-phase FIR filter. A novel hardware structure for single-bit input digital filters is proposed. The proposed structure was found to be competitive and was used for the implementation. The decimator filter was successfully implemented in a 0.18 mm CMOS process using standard cells. In the third part of the thesis we discuss efficient realization of sum-of-products and multiple-constant multiplications that are used in, for example, FIR filters. We propose several new difference methods that result in realizations with a low number of adders. The proposed design methods have low complexity, i.e., they can be included in the search for quantized filter coefficients.