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A finite element tool has been developed to design and investigate a multi-hull composite ship structure, and a hybrid hull of identical length and beam. Hybrid hull structure is assembled by Titanium alloy (Ti-6Al-4V) frame and sandwich composite panels. Wave loads and slamming loads acting on both hull structures have been calculated according to ABS rules at sea state 5 with a ship velocity of 40 knots. Comparisons of deformations and stresses between two sets of loadings demonstrate that slamming loads have more detrimental effects on ship structure. Deformation under slamming is almost one order higher than that caused by wave loads. Also, Titanium frame in hybrid hull significantly reduces both deformation and stresses when compared to composite hull due to enhancement of in plane strength and stiffness of the hull. A 73m long hybrid hull has also been investigated under wave and slamming loads in time domain for dynamic analysis. / Includes bibliography. / Thesis (M.S.)--Florida Atlantic University, 2013.

In recent years, with only small fractions of modern processors now accessible in a single cycle, computer architects constantly fight against propagation issues across the die. Unfortunately this trend continues to shift inward, and now the even most internal features of the pipeline are designed around communication, not computation. To address the inward creep of this constraint, this work focuses on the characterization of communication within the pipeline itself, architectural techniques to avoid it when possible, and layout co-design for early detection of problems. I present work in creating a novel detection tool for common case operand movement which can rapidly characterize an applications dataflow patterns. The results produced are suitable for exploitation as a small number of patterns can describe a significant portion of modern applications. Work on dynamic dependence collapsing takes the observations from the pattern results and shows how certain groups of operations can be dynamically grouped, avoiding unnecessary communication between individual instructions. This technique also amplifies the efficiency of pipeline data structures such as the reorder buffer, increasing both IPC and frequency. I also identify the same sets of collapsible instructions at compile time, producing the same benefits with minimal hardware complexity. This technique is also done in a backward compatible manner as the groups are exposed by simple reordering of the binarys instructions. I present aggressive pipelining approaches for these resources which avoids the critical timing often presumed necessary in aggressive superscalar processors. As these structures are designed for the worst case, pipelining them can produce greater frequency benefit than IPC loss. I also use the observation that the dynamic issue order for instructions in aggressive superscalar processors is predictable. Thus, a hardware mechanism is introduced for caching the wakeup order for groups of instructions efficiently. These wakeup vectors are then used to speculatively schedule instructions, avoiding the dynamic scheduling when it is not necessary. Finally, I present a novel approach to fast and high-quality chip layout. By allowing architects to quickly evaluate what if scenarios during early high-level design, chip designs are less likely to encounter implementation problems later in the process.

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To build for living is to understand that built form exists only in relationship to the life that occupies it and that human life is better when it is in constant interaction with the built environment; we design it, build it, and change it as we design, build, and change our selves. Making your own place and changing it over time is an important component of living one's life to its fullest. To explore these issues, designs were made for an adaptable building type - the "mountain hut," a temporary accommodation for its wandering inhabitants. Designing it twice, as well as relocating the initial building type across the globe, from the mountains of Sierra Nevada to the Himalayas in Nepal, provided an opportunity to compare and understand the influences of local environmental and cultural conditions on the building's adaptability, as well as the level of interactivity its inhabitants could experience as they occupied and transformed the dwelling. Both designs incorporate sustainable design principles, which strengthen the overall comparison of climatic responses and the use of local materials and building technologies. / Department of Architecture

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Architecture, 1991. / Odd-number pages numbered; even number pages blank. Pages 170 and 171 blank. / Includes bibliographical references. / The intent of this work was to explore an additive working method as a way to generate building form. It was initiated without any preconceived ideas about the project's final outcome. Instead, it focused on observations, associations, and attitudes of existing experiences and information. Working from the position that "one perception must immediately and directly lead to a further perception," a decisions were made. The design of an elementary school was the vehicle for the process. / by Mark Daley. / M.S.

A research report submitted to the Faculty of Engineering and the Built Environment, University of the Witwatersrand, Johannesburg, in partial fulfilment of the requirements for the degree of Master of Science in Engineering. Johannesburg 2017 / The present study investigates the possibility of designing a catenary barrel vault, which can be implemented in regions where extreme tropical storms are frequently experienced. It moreover investigated the effect of non-uniform wind loads on catenary barrel vaults, and how to solve for these load conditions efficiently. The effects of high, non-uniform wind loads were assessed, and possible solutions were explored to determine a structurally efficient solution in resisting the loads applied. Different analysis and design techniques were explored in this research. These techniques included the optimization of the geometry, in resisting the applied loads most efficiently, as well as the structural design of the section in ensuring a durable and safe structure. The study revealed that the geometry of the structure cannot be optimised to resist the applied loads in a catenary fashion without external aid. By draping the vault in a post-tensioned basalt geogrid mesh, axial compression can be increased in the section and geometry optimisation can be achieved in resisting the applied loads in a catenary fashion. Three post-tensioning techniques were investigated and discussed. / MT 2018

Power consumption is a major concern for modern processors. Voltage scaling is one of the most effective mechanisms to reduce power consumption. However, voltage scaling is limited by large memory structures, such as caches, where many cells can fail at low voltage operation. As a result, voltage scaling is limited by a minimum voltage (Vccmin), below which the processor may not operate reliably. Researchers have proposed architectural mechanisms, error detection and correction techniques, and circuit solutions to allow the cache to operate reliably at low voltages. Architectural solutions reduce cache capacity at low voltages at the expense of logic complexity. Circuit solutions change the SRAM cell organization and have the disadvantage of reducing the cache capacity (for the same area) even when the system runs at a high voltage. Error detection and correction mechanisms use Error Correction Codes (ECC) codes to keep the cache operation reliable at low voltage, but have the disadvantage of increasing cache access time. In this thesis, we propose a novel architectural technique that uses spare cache blocks to back up a set-associative cache at low voltage. In our mechanism, we perform memory tests at low voltage to detect errors in all cache lines and tag them as faulty or fault-free. We have designed shifter and adder circuits for our architecture, and evaluated our design using the SimpleScalar simulator. We constructed a fault model for our design to find the cache set failure probability at low voltage. Our evaluation shows that, at 485mV, our designed cache operates with an equivalent bit failure probability to a conventional cache operating at 782mV. We have compared instructions per cycle (IPC), miss rates, and cache accesses of our design with a conventional cache operating at nominal voltage. We have also compared our cache performance with a cache using the previously proposed Bit-Fix mechanism. Our result show that our designed spare cache mechanism is 15% more area efficient compared to Bit-Fix. Our proposed approach provides a significant improvement in power and EPI (energy per instruction) over a conventional cache and Bit-Fix, at the expense of having lower performance at high voltage.