Irritable Bowel Syndrome (IBS) is one of the most common functional disorders of the gastrointestinal tract. Visceral hypersensitivity is the most commonly reported symptom of IBS, yet is the least adequately treated. Mechanosensitive information from the colon is relayed to the CNS by extrinsic colonic primary afferent nerves which have their cell bodies within dorsal root ganglia (DRG). This thesis aims to identify the contribution of several putatively mechanosensitive ion channels (ASIC1, 2 and 3, TRPV4 and TRPA1) toward detection of mechanical stimuli in the colon. This involvement is assessed by both molecular and functional means. The abundance of each of these channels was assessed by comparing expression within whole DRG against that in specifically colonic DRG neurons using an in situ hybridization methodology developed as part of this PhD. The functional role TRPV4 and TRPA1 impart toward colonic mechanosensation was investigated by recording responses to mechanical stimuli from colonic primary afferent fibres and comparing the results from mice genetically modified to lack either TRPV4 or TRPA1 with those of their intact littermates. The results from these studies indicate expression patterns within whole DRG do not provide accurate representation of the organ of interest, with abundances of each of the channels investigated differing between colonic DRG cells and the whole DRG. In particular ASIC3 and TRPV4 are preferentially expressed in colonic DRG neurons, unlike ASIC2 and TRPA1. Further, TRPV4 is functionally restricted to detection of noxious mechanical stimuli in the colon, while expression of TRPA1 is more widespread and functionally less restricted. Each of these channels are each potential targets for the treatment of IBS as each affects specific aspects of colonic mechanotransduction. / http://proxy.library.adelaide.edu.au/login?url= http://library.adelaide.edu.au/cgi-bin/Pwebrecon.cgi?BBID=1347202 / Thesis (Ph.D.) - University of Adelaide, School of Molecular and Biomedical Sciences, 2008

In the industry of intellectual property products "IP-cores", a communication link is almost always needed. A semiconductor intellectual property IP core is a reusable unit of logic in electronic design. IP cores are used as building blocks for ASIC chip design or FPGA logic designs. A bus creates a communication link between the IP cores in a system. The company AnaCatum Design AB have many projects where a bus is needed. Creating a new bus structure for every project is time consuming. By having a generic bus structure of a known standard with changeable parameters, the user only has to set the desired parameters to fit the system. Also having interfaces for master and slave the user has only to make minor changes to have a fully functional bus for the system.

O avanço da microeletrônica nas últimas décadas trouxe maior densidade aos circuitos integrados, possibilitando a implementação de funções de alta complexidade em uma menor área de silício. Como efeito desta integração em larga escala, as latências dos fios passaram a representar uma maior fração do atraso de propagação de dados em um design, tornando a tarefa de “timing closure” mais desafiadora e demandando mais iterações entre etapas do design. Por meio de uma revisão na teoria dos circuitos insensíveis a latência (Latency-Insensitive theory), este trabalho explora a metodologia de designs elásticos (Elastic Design methodology) em circuitos síncronos, com o objetivo de solucionar o impacto que a latência adicional dos fios insere no fluxo de design de circuitos integrados, sem demandar uma grande mudança de paradigma por parte dos designers. A fim de exemplificar o processo de “elasticização”, foi implementada uma versão síncrona da arquitetura do microprocessador Neander que posteriormente foi convertida a um Circuito Elástico utilizando um protocolo insensível a latência nas transferências de dados entre os processos computacionais do design. Ambas as versões do Neander foram validadas em uma plataforma FPGA utilizando ferramentas e fluxo de design síncrono bem estabelecidos. A comparação das características de timing e área entre os designs demonstra que a versão Elástica pode apresentar ganhos de performance para sistemas complexos ao custo de um aumento da área necessária. Estes resultados mostram que a metodologia de designs elásticos é uma boa candidata para projetar circuitos integrados complexos sem demandar custosas iterações entre fases de design e reutilizando as já estabelecidas ferramentas de design síncrono, resultando em uma alternativa economicamente vantajosa para os designers. / The advance of microelectronics brought increased density to integrated circuits, allowing high complexity functions to be implemented in smaller silicon areas. As a side effect of this large-scale integration, the wire latencies became a higher fraction of a design’s data propagation latency, turning timing closure into a challenging task that often demand several iterations among design phases. By reviewing the Latency-Insensitive theory, this work presents the exploration of the Elastic Design methodology in synchronous circuits, with the objective of solving the increased wire latency impact on integrated circuits design flow without requiring a big paradigm change for designers. To exemplify the elasticization process, the educational Neander microprocessor architecture is synchronously implemented and turned into an Elastic Circuit by using a latency-insensitive protocol in the design’s computational processes data transfers. Both designs are validated in an FPGA platform, using well known synchronous design tools and flow. The timing and area comparison between the designs demonstrates that the Elastic version can present performance advantages for more complex systems at the price of increased area. These results show that the Elastic Design methodology is a good candidate for designing complex integrated circuits without costly iterations between design phases. This methodology also leverages the reuse of the mostly adopted synchronous design tools, resulting in a cost-effective alternative for designers.

Os efeitos de radiação têm sido um dos problemas mais sérios em aplicações militares e espaciais. Mas eles também são uma preocupação crescente em tecnologias modernas, mesmo para aplicações comerciais no nível do solo. A proteção dos circuitos integrados contra os efeitos da radiação podem ser obtidos através do uso de processos de fabricação aprimorados e de estratégias em diferentes estágios do projeto do circuito. A técnica de TMR é bem conhecida e amplamente empregada para mascarar falhas únicas sem detectálas. No entanto, o projeto de circuitos TMR não é automatizado por ferramentas EDA comerciais e até mesmo eles podem remover parcial ou totalmente a lógica redundante. Por outro lado, existem várias ferramentas que podem ser usadas para implementar a técnica de TMR em circuitos integrados, embora a maioria delas sejam ferramentas comerciais licenciadas, convenientes apenas para dispositivos específicos, ou com uso restrito por causa do regime ITAR. O presente trabalho pretende superar esses incovenientes, para isso uma metodologia é proposta para automatizar o projeto de circuitos TMR utilizando um fluxo de projeto comercial. A abordagem proposta utiliza um netlist estruturado para implementar automaticamente os circuitos TMR em diferentes níveis de granularidade de redundância para projetos baseados em células e FPGA. A otimização do circuito TMR resultante também é aplicada com base na abordagem do dimensionamento de portas lógicas. Além disso, a verificação do circuito TMR implementado é baseada na verificação de equivalência e garante sua funcionalidade correta e sua capacidade de tolerancia a falhas simples. Experimentos com um circuito derivado de HLS e uma descrição ofuscada do soft-core ARM Cortex-M0 foram realizados para mostrar o uso e as vantagens do fluxo de projeto proposto. Diversas questões relacionadas à remoção da lógica redundante implementada foram encontradas, bem como o impacto no incremento de área causado pelos votadores de maioria. Além disso, a confiabilidade de diferentes implementações de TMR do soft core ARM sintetizado em FPGA foi avaliada usando campanhas de injeção de falhas emuladas. Como resultado, foi reforçado o nível de alta confiabilidade da implemntação com mais fina granularidade, mesmo na presença de até 10 falhas acumuladas, e a menor capacidade de mitigação correspondente à replicação de flip-flops apenas. / Radiation effects have been one of the most serious issues in military and space applications. But they are also an increasing concern in modern technologies, even for commercial applications at the ground level. Protection or hardening of integrated circuits against radiation effects can be obtained through the use of enhanced fabrication processes and strategies at different stages of the circuit design. The triple modular redundancy (TMR) technique is a widely and well-known technique employed to mask single faults without detecting them. However, the design of TMR circuits is not automated by commercial electronic design automation (EDA) tools and even they can remove partially or totally the redundant logic. On the other hand, there are several tools that can be used to implement the TMR technique in integrated circuits, although most of them are licensed commercial tools, convenient only for specific devices, or with restricted use because of the International Traffic in Arms Regulations (ITAR) regimen. The present work intends to overcome these issues so a methodology is proposed to automate the design of TMR circuits using a commercial design flow. The proposed approach uses a structured netlist to implement automatically TMR circuits at different granularity levels of redundancy for cell-based and field-programmable gate array (FPGA) designs. Optimization of the resulting TMR circuit is also applied based on the gate sizing approach. Moreover, verification of the implemented TMR circuit is based on equivalence checking, and guarantee its correct functionality and its fault-tolerant capability against soft errors. Experiments with an high-level synthesis (HLS)-derived circuit and an obfuscated description of the ARM Cortex-M0 soft-core are performed to show the use and the advantages of the proposed design flow. Several issues related to the removal of the implemented redundant logic were found as well as the impact in the increment of area caused by the majority voters. Furthermore, the reliability of different TMR implementations of the ARM soft-core synthesized in FPGA was evaluated using emulated-simulation fault injection campaigns. As a result, it was reinforced the high-reliability level of the finest granularity implementation even in the presence of up to 10 accumulated faults and the poorest mitigation capacity corresponding to the replication of flip-flops solely.

abstract: Improving energy efficiency has always been the prime objective of the custom and automated digital circuit design techniques. As a result, a multitude of methods to reduce power without sacrificing performance have been proposed. However, as the field of design automation has matured over the last few decades, there have been no new automated design techniques, that can provide considerable improvements in circuit power, leakage and area. Although emerging nano-devices are expected to replace the existing MOSFET devices, they are far from being as mature as semiconductor devices and their full potential and promises are many years away from being practical. The research described in this dissertation consists of four main parts. First is a new circuit architecture of a differential threshold logic flipflop called PNAND. The PNAND gate is an edge-triggered multi-input sequential cell whose next state function is a threshold function of its inputs. Second a new approach, called hybridization, that replaces flipflops and parts of their logic cones with PNAND cells is described. The resulting \hybrid circuit, which consists of conventional logic cells and PNANDs, is shown to have significantly less power consumption, smaller area, less standby power and less power variation. Third, a new architecture of a field programmable array, called field programmable threshold logic array (FPTLA), in which the standard lookup table (LUT) is replaced by a PNAND is described. The FPTLA is shown to have as much as 50% lower energy-delay product compared to conventional FPGA using well known FPGA modeling tool called VPR. Fourth, a novel clock skewing technique that makes use of the completion detection feature of the differential mode flipflops is described. This clock skewing method improves the area and power of the ASIC circuits by increasing slack on timing paths. An additional advantage of this method is the elimination of hold time violation on given short paths. Several circuit design methodologies such as retiming and asynchronous circuit design can use the proposed threshold logic gate effectively. Therefore, the use of threshold logic flipflops in conventional design methodologies opens new avenues of research towards more energy-efficient circuits. / Dissertation/Thesis / Doctoral Dissertation Computer Science 2015

O avanço da microeletrônica nas últimas décadas trouxe maior densidade aos circuitos integrados, possibilitando a implementação de funções de alta complexidade em uma menor área de silício. Como efeito desta integração em larga escala, as latências dos fios passaram a representar uma maior fração do atraso de propagação de dados em um design, tornando a tarefa de “timing closure” mais desafiadora e demandando mais iterações entre etapas do design. Por meio de uma revisão na teoria dos circuitos insensíveis a latência (Latency-Insensitive theory), este trabalho explora a metodologia de designs elásticos (Elastic Design methodology) em circuitos síncronos, com o objetivo de solucionar o impacto que a latência adicional dos fios insere no fluxo de design de circuitos integrados, sem demandar uma grande mudança de paradigma por parte dos designers. A fim de exemplificar o processo de “elasticização”, foi implementada uma versão síncrona da arquitetura do microprocessador Neander que posteriormente foi convertida a um Circuito Elástico utilizando um protocolo insensível a latência nas transferências de dados entre os processos computacionais do design. Ambas as versões do Neander foram validadas em uma plataforma FPGA utilizando ferramentas e fluxo de design síncrono bem estabelecidos. A comparação das características de timing e área entre os designs demonstra que a versão Elástica pode apresentar ganhos de performance para sistemas complexos ao custo de um aumento da área necessária. Estes resultados mostram que a metodologia de designs elásticos é uma boa candidata para projetar circuitos integrados complexos sem demandar custosas iterações entre fases de design e reutilizando as já estabelecidas ferramentas de design síncrono, resultando em uma alternativa economicamente vantajosa para os designers. / The advance of microelectronics brought increased density to integrated circuits, allowing high complexity functions to be implemented in smaller silicon areas. As a side effect of this large-scale integration, the wire latencies became a higher fraction of a design’s data propagation latency, turning timing closure into a challenging task that often demand several iterations among design phases. By reviewing the Latency-Insensitive theory, this work presents the exploration of the Elastic Design methodology in synchronous circuits, with the objective of solving the increased wire latency impact on integrated circuits design flow without requiring a big paradigm change for designers. To exemplify the elasticization process, the educational Neander microprocessor architecture is synchronously implemented and turned into an Elastic Circuit by using a latency-insensitive protocol in the design’s computational processes data transfers. Both designs are validated in an FPGA platform, using well known synchronous design tools and flow. The timing and area comparison between the designs demonstrates that the Elastic version can present performance advantages for more complex systems at the price of increased area. These results show that the Elastic Design methodology is a good candidate for designing complex integrated circuits without costly iterations between design phases. This methodology also leverages the reuse of the mostly adopted synchronous design tools, resulting in a cost-effective alternative for designers.

Os efeitos de radiação têm sido um dos problemas mais sérios em aplicações militares e espaciais. Mas eles também são uma preocupação crescente em tecnologias modernas, mesmo para aplicações comerciais no nível do solo. A proteção dos circuitos integrados contra os efeitos da radiação podem ser obtidos através do uso de processos de fabricação aprimorados e de estratégias em diferentes estágios do projeto do circuito. A técnica de TMR é bem conhecida e amplamente empregada para mascarar falhas únicas sem detectálas. No entanto, o projeto de circuitos TMR não é automatizado por ferramentas EDA comerciais e até mesmo eles podem remover parcial ou totalmente a lógica redundante. Por outro lado, existem várias ferramentas que podem ser usadas para implementar a técnica de TMR em circuitos integrados, embora a maioria delas sejam ferramentas comerciais licenciadas, convenientes apenas para dispositivos específicos, ou com uso restrito por causa do regime ITAR. O presente trabalho pretende superar esses incovenientes, para isso uma metodologia é proposta para automatizar o projeto de circuitos TMR utilizando um fluxo de projeto comercial. A abordagem proposta utiliza um netlist estruturado para implementar automaticamente os circuitos TMR em diferentes níveis de granularidade de redundância para projetos baseados em células e FPGA. A otimização do circuito TMR resultante também é aplicada com base na abordagem do dimensionamento de portas lógicas. Além disso, a verificação do circuito TMR implementado é baseada na verificação de equivalência e garante sua funcionalidade correta e sua capacidade de tolerancia a falhas simples. Experimentos com um circuito derivado de HLS e uma descrição ofuscada do soft-core ARM Cortex-M0 foram realizados para mostrar o uso e as vantagens do fluxo de projeto proposto. Diversas questões relacionadas à remoção da lógica redundante implementada foram encontradas, bem como o impacto no incremento de área causado pelos votadores de maioria. Além disso, a confiabilidade de diferentes implementações de TMR do soft core ARM sintetizado em FPGA foi avaliada usando campanhas de injeção de falhas emuladas. Como resultado, foi reforçado o nível de alta confiabilidade da implemntação com mais fina granularidade, mesmo na presença de até 10 falhas acumuladas, e a menor capacidade de mitigação correspondente à replicação de flip-flops apenas. / Radiation effects have been one of the most serious issues in military and space applications. But they are also an increasing concern in modern technologies, even for commercial applications at the ground level. Protection or hardening of integrated circuits against radiation effects can be obtained through the use of enhanced fabrication processes and strategies at different stages of the circuit design. The triple modular redundancy (TMR) technique is a widely and well-known technique employed to mask single faults without detecting them. However, the design of TMR circuits is not automated by commercial electronic design automation (EDA) tools and even they can remove partially or totally the redundant logic. On the other hand, there are several tools that can be used to implement the TMR technique in integrated circuits, although most of them are licensed commercial tools, convenient only for specific devices, or with restricted use because of the International Traffic in Arms Regulations (ITAR) regimen. The present work intends to overcome these issues so a methodology is proposed to automate the design of TMR circuits using a commercial design flow. The proposed approach uses a structured netlist to implement automatically TMR circuits at different granularity levels of redundancy for cell-based and field-programmable gate array (FPGA) designs. Optimization of the resulting TMR circuit is also applied based on the gate sizing approach. Moreover, verification of the implemented TMR circuit is based on equivalence checking, and guarantee its correct functionality and its fault-tolerant capability against soft errors. Experiments with an high-level synthesis (HLS)-derived circuit and an obfuscated description of the ARM Cortex-M0 soft-core are performed to show the use and the advantages of the proposed design flow. Several issues related to the removal of the implemented redundant logic were found as well as the impact in the increment of area caused by the majority voters. Furthermore, the reliability of different TMR implementations of the ARM soft-core synthesized in FPGA was evaluated using emulated-simulation fault injection campaigns. As a result, it was reinforced the high-reliability level of the finest granularity implementation even in the presence of up to 10 accumulated faults and the poorest mitigation capacity corresponding to the replication of flip-flops solely.

Depuis une vingtaine d'années, le GRAMS et le CIMS travaillent en collaboration dans le domaine de l'imagerie médicale, plus précisément sur la tomographie d'émission par positrons destinée à la recherche préclinique sur petits animaux. Après le scanner TEP Sherbrooke en 1994 et le LabPET I commercialisé par Advanced Molecular Imaging (AMI) Inc., Gamma Medica Ideas et GE Healthcare au cours des années 2000, l'aspiration vers de meilleures performances est le moteur de la réalisation d'une nouvelle version : le LabPET II. L'augmentation importante du nombre de détecteurs, nécessaire pour atteindre une meilleure résolution spatiale, amène de nouveaux défis autant sur le plan matériel que logiciel. Un des défis est de compenser les disparités en gain des détecteurs à base de photodiodes à avalanche (PDA) qui engendrent des différences intercanaux. Le but de ce projet de maîtrise est de développer et d'implémenter un algorithme capable de corriger ces différences de façon automatisée.

Cette thèse s'inscrit dans le cadre de la mission Sino-française SVOM (Space-based multi-band Variable Object Monitor) dédiée à l'étude des sursauts gamma à l'horizon 2020. Ces explosions cosmologiques très intenses apparaissent aléatoirement sur le ciel comme des bouffées de photons très brèves (de quelques milli-secondes à quelques minutes). Ils sont engendrés par la formation catastrophique de trous noirs dans le cœur de certaines étoiles massives en effondrement gravitationnel ou par la coalescence de deux objets compacts et se caractérisent par de puissants jets ultra-relativistes orientés vers la Terre. SVOM permettra d'étudier la nature des progéniteurs, les mécanismes d'accélération des particules et les processus d'émission associés, la géométrie des jets et leurs compositions. Le satellite implémentera une charge utile multi-longueur d'onde dont le cœur sera la caméra grand-champ à masque codé, ECLAIRs, en charge de la détection et de la localisation des sursauts gamma entre 4 et 150 keV. Ma thèse a pour objectif de caractériser les performances scientifiques des modules de détection XRDPIX (i.e. un hybride de 8x4 détecteurs couplés à une électronique bas bruit) qui paveront le plan de détection, DPIX, de la caméra. Pour ce faire, je discute ma méthodologie pour caractériser les impacts des paramètres instrumentaux sur les performances des XRDPIX en me basant sur les résultats des nombreuses campagnes de tests que j'ai menées sur plusieurs modules au moyen d'un banc de test vide-thermique dédié et de sources radioactives. J'étudie la contribution des différentes sources de bruit en développant un modèle me permettant de contrôler la qualité du processus d'hybridation des détecteurs avec leur électronique de proximité. Je délimite la zone de fonctionnement optimale pour le vol des modules de détection en étudiant statistiquement l'impact des différents paramètres instrumentaux sur leur bruit et leur efficacité de comptage. Je mets en évidence l'apparition de comportements instables sur quelques voies dans certaines configurations. Je discute le protocole expérimental mis en place pour caractériser la nature de ces instabilités ainsi que les solutions envisagées. J'optimise les critères de sélection des détecteurs pour le modèle de vol à partir de mesures spectroscopiques et de courant de fuite effectuées sur une population de 12000 détecteurs. Finalement, je présente les résultats d'essais réalisés à l'accélérateur TANDEM pour caractériser l'impact des particules chargées (protons de 20 MeV et particules alpha de 30 MeV) sur la chaine électronique d'ECLAIRs. / Gamma-ray bursts (GRBs) are short and very intense flashes of X-/gamma-ray photons lasting from few milliseconds to hundreds of seconds appearing randomly over the sky. These cosmological events are thought to be due to the catastrophic formation of newly formed black holes following the collapse of some massive stars or after the coalescence of two compact objects and resulting in the launch of powerful ultra-relativistic jets orientated towards the Earth. The Sino-French mission SVOM (Space-based multi-band Variable Object Monitor) is dedicated to the study of these extreme and fascinating transient events and expected to be launched in 2020s. The satellite will implement a multi-wavelength science payload amongst which the core will be the large-field coded-mask camera ECLAIRs in charge of the detection and the localisation of GRBs in the 4-150 keV range. The ECLAIRs detection plane, DPIX, is made of 80x80 Schottky CdTe semi-conductor detectors and the front-end electronics. During my PhD, I mainly worked on the characterization of the scientific performance of the elementary detection modules called XRDPIX (i.e. a hybrid made of 8x4 detectors coupled with a low-noise ASIC) that will paved the DPIX. The main goal is then to derive the best suitable choice of the instrumental parameters in order to optimize the camera in-flight performance. In the manuscript, I discuss the methodology I used to explore the instrument parameter space. I describe the various testing protocoles that I created and the different tests that I performed using several XRDPIX modules in a thermal-vacuum chamber and irradiated with radioactive sources. I discuss in detail the results and the various observables that I used to define the optimal in-flight operating zone of the detection plane. I also study the contribution of the different noise sources coming from the detectors and the electronic chain with a model I designed in order to control the quality of the hybridization process. I also highlight evidence for instable behaviors of some XRDPIX channels. I describe the experiments performed in order to investigate their nature and I discuss the possible solutions to mitigate their impacts of the overall XRDPIX performance. Finally, I study the impact of particles on the ECLAIRs X/?-ray camera electronic chain.

This thesis investigates the use of massively parallel fine-grained processor arrays to increase computational performance. As processors move towards multi-core processing, more energy-efficient processors can be designed by increasing the number of processor cores on a single chip rather than increasing the clock frequency of a single processor. This can be done by making processor cores less complex, but increasing the number of processor cores on a chip. Using this philosophy, a processor core can be reduced in complexity, area, and speed to form a very small processor which can still perform basic arithmetic operations. Due to the small area occupation this can be multiplied and scaled to form a large scale parallel processor array to offer a significant performance. Following this design methodology, two fine-grained parallel processor arrays are designed which aim to achieve a small area occupation with each individual processor so that a larger array can be implemented over a given area. To demonstrate scalability and performance, SIMD parallel processor array is designed for implementation on an FPGA where each processor can be implemented using four ‘slices’ of a Xilinx FPGA. With such small area utilization, a large fine-grained processor can be implemented on these FPGAs. A 32 × 32 processor array is implemented and fast processing demonstrated using image processing tasks. An event-driven MIMD parallel processor array is also designed which occupies a small amount of area and can be scaled up to form much larger arrays. The event-driven approach allows the processor to enter an idle mode when no events are occurring local to the processor, reducing power consumption. The processor can switch to operational mode when events are detected. The processor core is designed with a multi-bit data path and ALU and contains its own instruction memory making the array a multi-core processor array. With area occupation of primary concern, the processor is relatively simple and connects with its four nearest direct neighbours. A small 8 × 8 prototype chip is implemented in a 65 nm CMOS technology process which can operate at a clock frequency of 80 MHz and offer a peak performance of 5.12 GOPS which can be scaled up to larger arrays. An application of the event-driven processor array is demonstrated using a simulation model of the processor. An event-driven algorithm is demonstrated to perform distributed control of distributed manipulator simulator by separating objects based on their physical properties.