Threshold logic gates have the capability of realizing complex Boolean functions with smaller number of logic gates [1]. These gates are very sensitive to their weight values which may change during manufacturing process. So Threshold logic gates should be carefully designed to allow for maximum deviation from desired design weight values without affecting its functionality . This maximum allowable deviation is known as Fault Tolerance of the gate. ILP is one of the methods to find the optimum weight values with fault tolerance. But ILP has inability to solve the threshold functions with large inputs. This thesis presents two methods to overcome this difficulty.First one is the Combination method which combines the procedures of both decomposition method and ILP method .Second one is the Variable collapsing method which uses the principle of Variable Collapsing to find weights values with fault tolerance for large input functions.

Thesis (M.S.)--Rochester Institute of Technology, 1989. / "References": leaves 26-28.

Thesis (M.S.)--Rochester Institute of Technology, 1991. / Includes bibliographical references (leaves 106-111).

[by] A.K. Susskind, D.R. Haring [and] C.L. Liu. / Includes bibliographies. / "AD 657370."

Threshold logic gates are gaining more importance in recent years due to significant development in switching devices. This renewed the interest in high performance and low power circuits with threshold logic gates. Threshold Logic Gates can be implemented using both the traditional CMOS technologies and the emerging nanoelectronic technologies. In this dissertation, we have performed performance analysis on Monostable-Bistable Threshold Logic Element based, current mode, and memristor based threshold logic implementations. Existing analytical approaches that model the delay of a Monostable-Bistable Threshold Logic Element threshold logic gate cannot explore the enormous search space in the quest of weight assignments on the inputs and threshold in order to optimize the delay of the threshold logic gate. It is shown that this can be achieved by using a quantity that depends on the constants and Resonant Tunnel Diode weights. This quantity is used to form an integer linear program that optimizes the performance and ensure that each weight can tolerate a predetermined variation by an appropriate weight assignment in a threshold logic gate. The presented experimental results demonstrate the impact of the proposed method. The optimality of our solutions and the reported improvements ensure tolerance to potential manufacturing defects. Current mode is a popular CMOS-based implementation of threshold logic functions where the gate delay depends on the sensor size. A new implementation of current mode threshold functions for improved performance and switching energy is presented. An analytical method is also proposed in order to identify quickly the optimum sensor size. Experimental results on different gates with the optimum sensor size indicate that the proposed method outperforms consistently the existing implementations, and implements high performance and low power gates that have a very large number of inputs. A new dual clocked design that uses memristors in current mode logic implementation of threshold logic gates is also presented. Memristor based designs have high potential to improve performance and energy over purely CMOS-based combinational methods. The proposed designs are clocked, and outperform a recently proposed combinational method in performance as well as energy consumption. It is experimentally verified that both designs scale well in both energy consumption as well as delay.

Threshold logic gates allow for complex multi-input functions to be implemented using a single gate reducing the power and area of the circuit. Clocked based threshold gates have the additional advantage of its capability of being nanopipelined to increase network throughput. To produce a threshold network the proposed algorithm accepts a traditional algebraic boolean network as an input and resynthesizes it into a nanopipelined threshold logic network. The algorithm is the first to our knowledge that synthesizes in a manner to not only minimize the number of clusters produced from synthesizing the algebraic boolean network but also to minimize associated buffer insertion overhead in producing a clocked threshold gate network.

Shrinking minimum feature size in deep sub-micron has made fabrication of progressively faster devices possible. The performance of interconnects has been a bottleneck in determining the overall performance of a chip. A reliable high-speed communication technique is necessary to improve the performance of on-chip communication. Recent publications have demonstrated that use of multiple threshold voltages improves the performance of a bus significantly. The multi-threshold capture mechanism takes advantage of predictable temporal behavior of a tightly coupled bus to predict the next state of the bus early. However, Use of multiple threshold voltages also reduces the voltage slack and consequently increases the susceptibility to noise. Reduction in supply voltage exacerbates the situation. This work proposes a novel error detection and correction encoding technique that takes advantage of the high performance of the multi-threshold capture mechanism as well as its inbuilt redundancy to achieve reliable high-speed communication while introducing considerably less amount of redundancy as compared to the conventional methods. The proposed technique utilizes graph-based algorithms to produce a set of valid code words. The algorithm takes advantage of implicit set operations using binary decision diagram to improve the scalability of the code word selection process. The code words of many crosstalk avoidance codes including the proposed error detection and correction technique exhibit a highly structured behavior. The sets of larger valid code words can be recursively formed using the sets of smaller valid code words. This work also presents a generalized framework for scalable on-chip code word generation. The proposed CODEC implementation strategy uses a structured graph to model the recursive nature of an encoding technique that facilitates scalable CODEC implementation. The non-enumerative nature of the implementation strategy makes it highly scalable. The modular nature of the CODEC also simplifies use of pipelined architecture thereby improving the throughput of the bus.

Threshold Logic technology is conceived as the crucial alternate emerging technology to CMOS implementation in nanoelectronic era and the realization of complex functionalities is becoming an increasingly promising approach in the deep sub-micron design era. The gate that is implemented with threshold logic is called a Threshold Logic Gate (TLG). The logic output value of a Threshold Logic Gate (TLG) depends on the weighted sum of its inputs. Manufactured weights in the threshold logic gates (TLGs) may differ from the designed values and significantly affects the fault coverage. A novel fault model for weight defects is proposed. Also an Automatic Test Pattern Generation (ATPG) tool has been implemented that uses the fault model to detect whether the circuit is malfunctioning due to such weight-related defects. A novel design methodology is presented in this work to design complex TLG networks that are tolerant to manufacturing shortcomings. It uses a procedure to identify the optimum fault tolerant design of any given k-input TLG. Extensive research has been done in the development of synthesis methodologies in the past, predominantly greedy. A fault tolerance aware synthesis methodology is proposed.

[pt] A primeira parte deste trabalho consiste num estudo das desigualdades lineares que aparecem na síntese de funções lógicas por single-threshold. São desenvolvidas condições necessárias e suficientes para existência de solução, e também estabelecidas condições para a redução das desigualdades. Na segunda parte é proposto um método para calcular uma solução ótima para o sistema, sob certas condições de projeto. Finalmentesão apresentados métodos para realiza, com multithreshold devices, funções lógicas não realizáveis por single-threshold devices. / [en] The first part of this thesis is a theoretical study of sets of inequalities that appear in the synthesis of logical sufficient conditions are developd for existence of solution of the inequalities. In the second part, a numerical method for calculating proposed. Following this development, logical functions that cannot be realized by a single-threshold device are studied. Using the conditions developed before for single- threshold, methods are presented for realization of these functions by multithreshold devices.

Innovative nano-scale devices have been developed to enhance future circuit design to overcome physical barriers hindering complementary metal-oxide semiconductor (CMOS) technology. Among the emerging nanodevices, resonant tunneling diodes (RTDs) have demonstrated promising electronic features due to their high speed switching capability and functional versatility. Great circuit functionality can be achieved through integrating heterostructure field-effect transistors (HFETs) in conjunction with RTDs to modulate effective negative differential resistance (NDR). However, RTDs are intrinsically suitable for implementing threshold logic rather than Boolean logic which has dominated CMOS technology in the past. To fully take advantage of such emerging nanotechnology, efficient design methodologies and design automation tools for threshold logic therefore become essential. In this thesis, we first propose novel programmable logic elements (PLEs) implemented in threshold gates (TGs) and multi-threshold threshold gates (MTTGs) by exploring RTD/ HFET monostable-bistable transition logic element (MOBILE) principles. Our three-input PLE can be configured through five control bits to realize all the three-variable logic functions, which is, to the best of our knowledge, the first single RTD-based structure that provides complete logic implementation. It is also a more efficient reconfigurable circuit element than a general look-up table which requires eight configuration bits for three-variable functions. We further extend the design concept to construct a more versatile four-input PLE. A comprehensive comparison of three- and four-input PLEs provides an insightful view of design tradeoffs between performance and area. We present the mathematical proof of PLE's logic completeness based on Shannon Expansion, as well as the HSPICE simulation results of the programmable and primitive RTD/HFET gates that we have designed. An efficient control bit generating algorithm is developed by using a special encoding scheme to implement any given logic function. In addition, we propose novel techniques of formulating a given threshold logic in conjunctive normal form (CNF) that facilitates efficient SAT-based equivalence checking for threshold logic networks. Three different strategies of CNF generation from threshold logic representations are implemented. Experimental results based on MCNC benchmarks are presented as a complete comparison. Our hybrid algorithm, which takes into account input symmetry as well as input weight order of threshold gates, can efficiently generate CNF formulas in terms of both SAT solving time and CNF generating time. / Master of Science