É contínua a procura por técnicas de construção de circuitos que ajudem a minimizar os problemas existentes no mercado de microeletrônica atual. Uma alternativa para a resolução destes problemas consiste na utilização de circuitos assíncronos. Circuitos aritméticos são alvo de um contínuo esforço na busca de melhores resultados de desempenho e área. Em especial o somador é uma das partes constituintes desta classe de circuitos que apresenta interessante campo para pesquisas. Este trabalho apresenta um método de avaliação de somadores implementados através do uso de famílias lógicas CMOS dual-rail. Esta tarefa é realizada através do uso de um circuito assíncrono que serve como base de avaliação. Este circuito obedece ao protocolo de comunicação utilizado pelos somadores e nele são desenvolvidas diversas aplicações para que seja possível avaliar o comportamento dos somadores quando expostos a diferentes padrões de vetores. Os parâmetros avaliados nas estruturas dos somadores são número de transistores, atraso e consumo de potência para topologias carry look-ahead e ripple carry adders. Na avaliação dos somadores através de simulação elétrica são utilizadas as ferramentas Pspice e Spectre da Cadence. As tecnologias utilizadas nesta caracterização são AMI 0.5 da MOSIS e AMS 0.35. Como resultados são apresentados dados que demonstram a economia no número de transistores obtida através do uso da técnica de múltiplas saídas para o CLA, que a família DCVS geralmente apresenta os menores atrasos médios quando comparada a outras estruturas e a potencialidade de famílias NCL. / The search for construction techniques of circuits that helps to minimize the challenges that occurs in nowadays microelectronic market is continuous. An alternative to solve great part of these problems is the use of asynchronous circuits. Arithmetic circuits are the target of a continuous effort in the pursuit of better results in terms of performance and area. Adder circuits in special compose a subset of this class of circuits that presents an interesting research field. This work presents an evaluation method for adders that where implemented through different dual-rail logic families. This task is accomplished through the use of asynchronous circuits used as an evaluation base. The asynchronous circuits implemented obey the communication protocol adopted by the adders and implement different applications. These applications are constructed with the finality of study the adder’s behavior when they are exposed to different vector patterns. The adder’s evaluated parameters are the number of transistors, delay and power consumption of topologies like Carry Look-ahead and Ripple Carry Adders. The electrical simulations were accomplished trough the use of Pspice and Cadence’s Spectre cad tools. MOSIS AMI 0.5 and AMS 0.35 transistor technologies were utilized in the electrical characterization of the adders. Some of the results obtained trough this work that could be cited are: the low transistor count presented for the Multiple Outputs CLA structures, the performance advantage of the DCVS family in relation to the other families and the evaluation of NCL logic family potentiality.

The traditional method of implementing SRAM in CMOS is via a six-transistor cell and five routing lines. If the number of transistors and the number of wires could be reduced, the packing density of the memory cells could be increased, and the area reduced. This document describes the design of an SRAM system based on a new four¬transistor SRAM cell. The primary design goal was to create a functional system, so that the relationship between reduced cell area and a potentially reduced system area could be investigated. A new write method and associated array structure has been used, and the design of the system parameters was accomplished using static noise margin theory. The power dissipation and percentage reduction in cell area have been improved over previous designs. The circuits to achieve the access to the cell have been designed and simulated. These include low-impedance driver circuits, that allow the power supply of the cell's devices to be individually modified to read and write the cell, and a current sense amplifier system to convert the output current to a digital voltage. These circuits allow complete and accurate control to be achieved, but a price is paid for the complexity in terms of layout area. The SRAM system emulates a standard SRAM, and could therefore be used to replace current SRAM implementations. The design was simulated on a system level, and found to operate correctly. Although it is outperformed by its six-transistor cell counterpart in terms of power dissipation, speed and layout area, the groundwork for defining further research and improving the characteristics of further designs has been laid. / Dissertation (MEng (Electronic Engineering))--University of Pretoria, 2002. / Electrical, Electronic and Computer Engineering / unrestricted

This paper presents the design of a reconfigurable asynchronous unit, called the pulsed quad-cell (PQ-cell), for conformal computing. The conformal computing vision is to create computational materials that can conform to the physical and computational needs of an application. PQ-cells, like cellular automata, are assembled into arrays with nearest neighbor communication and are capable of general computation. They operate asynchronously to minimize power consumption and to allow sealing without the limitations imposed by a global clock. Cell operations are stimulated by pulses which use two wires to encode a data bit. Cells are individually reconfirgurable to perform logic, move and store information, and coordinate parallel activity. The PQ-cell design targets a 0.25 μm CMOS technology. Simulation results show that a PQ-cell, when pulsed at 1.3 GHz, consumes 16.9 pJ per operation. Examples of self-timed multi-cell structures include a 98 MHz ring oscillator and a 385 MHz pipeline.

A DRAM communicates with a processing unit via two interfaces: a data interface and a command interface. In today's DRAMs, also known as synchronous DRAMs (SDRAMs), both interfaces use a clock to communicate with the processing unit. The clock times the communication between the processing unit and the SDRAM on both the data interface and the command interface. We propose a self-timed DRAM. The self-timed DRAM introduces more flexibility into the DRAM interface by eliminating the clock. The command interface and the data interface each communicate with the processing unit using a handshake protocol rather than a clock. This thesis presents the data interface between the self-timed DRAM and the processing unit. The proposed data interface is self-timed. The self-timed data interface allows the DRAM to deliver data to or accept data from the processing unit as the processing unit demands rather than on a schedule set from the command interface. The self-timed data interface is designed using GasP circuits and micropipeline circuits. The design is simulated in 180nm CMOs process technology using hspice. This thesis presents the effects of width mismatch on the self-timed data interface. The micropipeline is slightly faster than the GasP. Also, the thesis compares the self-timed DRAM data interface with synchronous DRAM for the data burst rate.

Library characterization and 'Static Timing Analysis' (STA) are widely used in the design of modern CMOS integrated circuits to confirm that critical timing constraints are met. While many commercial tools are available to do timing validation using library characterization and static timing analysis, their operation depends on calculations relative to a global synchronous clock. This thesis applies timing validation to circuits from which the global synchronous clock is absent, making application of commercial tools difficult. Previous work at the University of Southern California (USC) showed how to overcome the incompatibility of commercial STA tools for asynchronous circuits. This thesis shows how to overcome the incompatibility of library characterization with respect to asynchronous circuits, and ties the results into the STA solution of USC. The particular family of circuits considered in this thesis is called GasP. GasP circuits are light in area and light in power. They have demonstrated operation at about twice the throughput one would expect from conventional clocked circuits. This makes GasP circuits excellent candidates for modern many-core, concurrent network-on-chip and system-on-chip architectures. In part, GasP circuits achieve their performance advantages by using a `single-track' signaling protocol. Two GasP modules communicate with each other over a single wire. One module drives the wire up and a second module at the other end of the wire drives the wire down. This conflicts with the common assumption that wires are driven only from one end. As a result, special circuitry is needed to characterize a GasP library module. This thesis shows how to break a GasP module and its timing constraints into manageable pieces and how to simulate and collect the data relevant for characterization and static timing analysis. When combined with software tools for identifying the critical timing constraints, the results of this work will provide confidence in the correct operation of GasP circuits.

No description available.

Asynchronous design is a possible alternative design methodology that has the ability to alleviate issues associated with clock skew, power dissipation, and process and environmental variability among transistors, issues encountered in typical synchronous design methodologies. This investigation studies the implementation of two asynchronous models of the Texas Instruments MSP430 processor family using a logic system known as Null Convention Logic (NCL). The study also investigates two design styles of NCL: the data-driven and control-driven design styles. This example and others show that although there are tradeoffs in chip area and performance, the control-driven design style is a viable methodology that can lead to designs that are low in energy usage. The openMSP430 processor project is the baseline for the investigation as it is a mature open-source project. Silicon-proven multiple times and fully synthesizable, it parallels the original Texas Instruments family nearly cycle for cycle. UNCLE (Unified NCL Environment) is a toolset used to create comparable implementations of the openMSP430 architecture that are data-driven and control-driven in nature. This investigation shows that the control-driven implementation has a slightly larger chip area due to the complexity of the control path and its effects on the data path. While the control path has a lower area than the data-driven model due to area optimization, the data path of the control-driven version is larger than that of the data-driven model. Because of these issues of complexity in both the control and data paths, the performance of the model suffers as well, degrading from the already poor performance of the traditional data-driven NCL model. Along with the increase in chip area and the decrease in performance, the control-driven model sees a 50.2% average decrease in energy usage as compared to the data-driven model. As with most design choices in engineering, there are tradeoffs when using either design style of NCL. This investigation serves to allow designers to make a well-informed decision when deciding between the two.

Ping-Ki Tsang. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2000. / Includes bibliographical references (leaves 87-95). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgments --- p.iii / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivation and Aims --- p.1 / Chapter 1.2 --- Contributions --- p.3 / Chapter 1.3 --- Overview of the Thesis --- p.4 / Chapter 2 --- Asynchronous Logic g --- p.6 / Chapter 2.1 --- Motivation --- p.6 / Chapter 2.2 --- Timing Models --- p.9 / Chapter 2.2.1 --- Fundamental-Mode Model --- p.9 / Chapter 2.2.2 --- Delay-Insensitive Model --- p.10 / Chapter 2.2.3 --- QDI and Speed-Independent Models --- p.11 / Chapter 2.3 --- Asynchronous Signalling Protocols --- p.12 / Chapter 2.3.1 --- 2-phase Handshaking Protocol --- p.12 / Chapter 2.3.2 --- 4-phase Handshaking Protocol --- p.13 / Chapter 2.4 --- Data Representations --- p.14 / Chapter 2.4.1 --- Dual Rail Coded Data --- p.15 / Chapter 2.4.2 --- Bundled Data --- p.15 / Chapter 2.5 --- Previous Asynchronous Processors --- p.16 / Chapter 2.6 --- Summary --- p.20 / Chapter 3 --- The MSL16 Architecture --- p.21 / Chapter 3.1 --- RISC Machines --- p.21 / Chapter 3.2 --- Stack Machines --- p.23 / Chapter 3.3 --- Forth and its Applications --- p.24 / Chapter 3.4 --- MSL16 --- p.26 / Chapter 3.4.1 --- Architecture --- p.28 / Chapter 3.4.2 --- Instruction Set --- p.30 / Chapter 3.4.3 --- The Datapath --- p.32 / Chapter 3.4.4 --- Interrupts and Exceptions --- p.33 / Chapter 3.4.5 --- Implementing Forth primitives --- p.34 / Chapter 3.4.6 --- Code Density Estimation --- p.34 / Chapter 3.5 --- Summary --- p.35 / Chapter 4 --- Design Methodology --- p.37 / Chapter 4.1 --- Basic Notation --- p.38 / Chapter 4.2 --- Specification of MSL16A --- p.39 / Chapter 4.3 --- Decomposition into Concurrent Processes --- p.41 / Chapter 4.4 --- Separation of Control and Datapath --- p.45 / Chapter 4.5 --- Handshaking Expansion --- p.45 / Chapter 4.5.1 --- 4-Phase Handshaking Protocol --- p.46 / Chapter 4.6 --- Production-rule Expansion --- p.47 / Chapter 4.7 --- Summary --- p.48 / Chapter 5 --- Implementation --- p.49 / Chapter 5.1 --- C-element --- p.49 / Chapter 5.2 --- Mutual Exclusion Elements --- p.51 / Chapter 5.3 --- Caltech Asynchronous Synthesis Tools --- p.53 / Chapter 5.4 --- Stack Design --- p.54 / Chapter 5.4.1 --- Eager Stack Control --- p.55 / Chapter 5.4.2 --- Lazy Stack Control --- p.56 / Chapter 5.4.3 --- Eager/Lazy Stack Datapath --- p.53 / Chapter 5.4.4 --- Pointer Stack Control --- p.61 / Chapter 5.4.5 --- Pointer Stack Datapath --- p.62 / Chapter 5.5 --- ALU Design --- p.62 / Chapter 5.5.1 --- The Addition Operation --- p.63 / Chapter 5.5.2 --- Zero-Checker --- p.64 / Chapter 5.6 --- Memory Interface and Tri-state Buffers --- p.64 / Chapter 5.7 --- MSL16A --- p.65 / Chapter 5.8 --- Summary --- p.66 / Chapter 6 --- Results --- p.67 / Chapter 6.1 --- FPGA based implementation of MSL16 --- p.67 / Chapter 6.2 --- MSL16A --- p.69 / Chapter 6.2.1 --- A Comparison of 3 Stack Designs --- p.69 / Chapter 6.2.2 --- Evaluation of the ALU --- p.73 / Chapter 6.2.3 --- Evaluation of MSL16A --- p.74 / Chapter 6.3 --- Summary --- p.81 / Chapter 7 --- Conclusions --- p.83 / Chapter 7.1 --- Future Work --- p.85 / Bibliography --- p.87 / Publications --- p.95

In modern integrated circuits, one way to reduce power consumption is to turn off power to parts of the circuit when those are idle. This method is called power gating. This thesis presents a state-preserving technique to achieve power savings in GasP family of asynchronous circuits by turning off the power when the circuit is idle. The power control logic turns on the power in anticipation of the receiving data. The power control logic turns off the power when the stage is idle either because it is empty or because the pipeline is clogged. The low logical effort of GasP circuits makes just-in-time power gating possible on a stage-by-stage basis. A new latch called Lazy Latch is introduced in this thesis. The lazy latch preserves its output and permits power gating of its larger transistors. The lazy latch is power efficient because it drives strongly only when necessary. A new latch called Blended Latch is proposed in this thesis which blends the advantages of the Conventional latches and the Lazy latches. Performance of power gating is evaluated by comparing the power-gated pipeline against the non-power gated pipeline. Power savings achieved are dependent on the duty cycle of operation. The fact that just-in-time power gating achieves power savings after it is idle for a minimum of 106 cycles makes it useful in limited applications where a quick start is required after long idle times.

A novel microarchitecture and circuit design techniques are presented for an asynchronous datapath that not only exhibits an extremely high rate of performance, but is also energy efficient. A 0.5 um chip was fabricated and tested that contains test circuits for the asynchronous datapath. Results show an adder and multiplier design that due to the 2-dimensional bit pipelining techniques, speculative completion, dynamic asynchronous circuits, and bit-level reservation stations and reorder buffers can commit 16-bit additions and multiplications at 1 giga operation per second (GOPS). The synchronicity simulator is also shown that simulates the same architecture except at more modern transistor nodes showing adder and multiplier performances at up to 11.1 GOPS in a commerically available 65 nm process. When compared to other designs and results, these prove to be some of the fastest if not the fastest adders and multipliers to date. The chip technology also was tested down to supply voltages below threshold making it extremely energy efficient. The asynchronous architecture also allows more exotic technologies, which are presented. Learning digital circuits are presented whereby the current supplied to a digital gate can be dynamically updated with floating gate technology. Probabilistic digital signal processing is also presented where the probabilistic operation is due to the statistical delay through the asynchronous circuits. Results show successful image processing with probabilistic operation in the least significant bits of the datapath resulting in large performance and energy gains.