abstract: The continuing advancement of modulation standards with newer generations of cellular technology, promises ever increasing data rate and bandwidth efficiency. However, these modulation schemes present high peak to average power ratio (PAPR) even after applying crest factor reduction. Being the most power-hungry component in the radio frequency (RF) transmitter, power amplifiers (PA) for infrastructure applications, need to operate efficiently at the presence of these high PAPR signals while maintaining reasonable linearity performance which could be improved by moderate digital pre-distortion (DPD) techniques. This strict requirement of operating efficiently at average power level while being capable of delivering the peak power, made the load modulated PAs such as Doherty PA, Outphasing PA, various Envelope Tracking PAs, Polar transmitters and most recently the load modulated balanced PA, the prime candidates for such application. However, due to its simpler architecture and ability to deliver RF power efficiently with good linearity performance has made Doherty PA (DPA) the most popular solution and has been deployed almost exclusively for wireless infrastructure application all over the world. Although DPAs has been very successful at amplifying the high PAPR signals, most recent advancements in cellular technology has opted for higher PAPR based signals at wider bandwidth. This lead to increased research and development work to innovate advanced Doherty architectures which are more efficient at back-off (BO) power levels compared to traditional DPAs. In this dissertation, three such advanced Doherty architectures and/or techniques are proposed to achieve high efficiency at further BO power level compared to traditional architecture using symmetrical devices for carrier and peaking PAs. Gallium Nitride (GaN) based high-electron-mobility (HEMT) technology has been used to design and fabricate the DPAs to validate the proposed advanced techniques for higher efficiency with good linearity performance at BO power levels. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2018

Ad hoc networks represent the current de-facto alternative for infrastructure-less environments, due to their self-configuring and resilience characteristics. Ad hoc networks flexibility benefits, such as unrestrained computing, lack of centralisation, and ease of deployment at low costs, are tightly bound with relevant deficiencies such as limited resources and management difficulty. Ad hoc networks witnessed high attention from the research community due to the numerous challenges faced when deploying such a technology in real scenarios. Starting with the nature of the wireless environment, which raises significant transmission issues when compared with the wired counterpart, ad hoc networks require a different approach when addressing the data link problems. Further, the high packet loss due to wireless contention, independent of network congestion, requires a different approach when considering quality of service degradation and unfair channel resources distribution among competing flows. Although these issues have already been considered to some extent by researchers, there is still room to improve quality of service by reducing the effect of packet loss and fairly distributing the medium access among competing nodes. The aim of this thesis is to propose a set of mechanisms to alleviate the effect of packet loss and to improve fairness in ad hoc networks. A transport layer algorithm has been proposed to overcome the effects of hidden node collisions and to reduce the impact of wireless link contention by estimating the four hop delay and pacing packet transmissions accordingly. Furthermore, certain topologies have been identified, in which the standard IEEE 802.11 faces degradation in channel utilisation and unfair bandwidth allocation. Three link layer mechanisms have been proposed to tackle the challenges the IEEE 802.11 faces in the identified scenarios to impose fairness in ad hoc networks through fairly distributing channel resources between competing nodes. These mechanisms are based on monitoring the collision rate and penalising the greedy nodes where no competing nodes can be detected but interference exists, monitoring traffic at source nodes to police access to the channel where only source nodes are within transmission range of each other, and using MAC layer acknowledgements to flag unfair bandwidth allocation in topologies where only the receivers are within transmission range of each other. The proposed mechanisms have been integrated into a framework designed to adapt and to dynamically select which mechanism to adopt, depending on the network topology. It is important to note that the proposed mechanisms and framework are not alternatives to the standard MAC protocol but are an enhancement and are triggered by the failure of the IEEE 802.11 protocol to distribute the channel resources fairly. All the proposed mechanisms have been validated through simulations and the results obtained from the experiments show that the proposed schemes fairly distribute channel resources fairly and outperform the performance of the IEEE 802.11 protocol in terms of channel utilisation as well as fairness.

The explosive growth of the wireless market has increased the demand for low-cost, highly-integrated CMOS wireless transceivers. However, the implementation of CMOS RF power amplifiers remains a formidable challenge. The objective of this research is to demonstrate the feasibility of CMOS RF power amplifiers by compensating for the RF performance disadvantages of CMOS technology. This dissertation proposes a parallel-combining transformer (PCT) as an impedance-matching and output-combining network. The results of a comprehensive analysis show that the PCT is a suitable solution for watt-level output power generation in cellular applications. To achieve high output power and high efficiency, the work presented here entailed the design of a class-E switching power amplifier in a 0.18-μm CMOS technology for GSM applications and, with the suggested power amplifier design technique, successfully demonstrated a fully-integrated RF front-end consisting of a power amplifier and an antenna switch. This dissertation also proposed an efficiency enhancement technique at power back-off. In an effort to save current in the power back-off while satisfying the EVM requirements, a class-AB linear power amplifier was implemented in a 0.18-μm CMOS technology for WLAN and WiMAX applications using a PCT as well as an operation class shift between class-A and class-B. Thus, the research in this dissertation provides low-cost CMOS RF power amplifier solutions for commercial products used in mobile wireless communications.

High efficiency is an essential requirement for any system, where the energy can be saved with full retention of system performance. The power amplifier in modern mobile communications system consumes most of the supplied power through the dissipated power and the required cooling systems. However, as new services were added as features for the developed mobile generations, the required data rate has increased to fulfil the new requirements. In this case, the data should be sent with the allocated bandwidth, so complex modulation schemes are used to utilise the available bandwidth efficiently. Nevertheless, the modulated signal will have a Peak to Average Power Ratio (PAPR) which increases as the modulation complexity is increasing. In this case, the power amplifier should be backed off and designed to provide good linearity and efficiency over high PAPR. Among the efficiency enhancement techniques, the Doherty technique (Load modulation technique) is the simplest one, where no additional circuity nor signal processing is required. In this work, the theory of load modulation amplifiers is investigated through two asymmetrical Doherty Power Amplifiers (DPA) targeting 3.3-3.5 GHz were designed and fabricated using two transistors (25 W and 45 W). In addition, more compact load modulation amplifiers targeting sub 6-GHz bandwidth of 5G specifically 3.4-3.8 GHz is discussed including the theory of implementing these amplifiers, where different amplifier capabilities are explored. Each amplifier design was discussed in detail, in which the input and output matching networks were designed and tested in addition to the design of the stability circuit to make sure that the amplifier is stable and working according to the specified requirements. The fabricated circuits were evaluated practically using the available instrument test, whereas Microwave Office software was used for the simulation purpose, each amplifier was designed separately, where all the designed amplifiers were able to provide the targeted efficiency at different back-off power points. Besides, some additional factors that affect the designed load modulation amplifiers such as the effect of the harmonics at the back-off and mismatching the amplifier is discussed. / European Union’s Horizon 2020 research and innovation programme (SECRET)

L'OFDM (Orthogonal Frequency Division Multiplexing) garantit un compromis optimal entre la transmission haut débit et la robustesse vis-à-vis des canaux multitrajet avec évanouissement. Ce procédé de modulation présente une forte fluctuation de l'amplitude de son enveloppe complexe avec une augmentation du PAPR (Peak-to-Average Power Ratio). En émission, un PAPR élevé oblige l'amplificateur de puissance (PA) à travailler loin de sa zone de saturation afin que le signal d'entrée ne soit pas trop distordu. Par conséquence, le rendement du PA décroît avec une augmentation de sa consommation. Dans un contexte de portabilité (ressource énergétique limitée), l'utilisation de modulations multiporteuses nécessite d'un traitement afin de minimiser cette consommation. La thèse s'insère alors dans ce contexte d'optimisation de la consommation tout en gardant une très bonne qualité du signal reçu. La méthode de réduction du PAPR dite d'écrêtage plus filtrage a été améliorée en donnant lieu à la nouvelle méthode d'écrêtage inversible. Ce système se compose de l'écrêtage « soft » pour la réduction du PAPR, du filtrage pour une ACPR (Adjacent Channel Power Ratio) acceptable et de l'inversion pour compenser les distorsions dues à l'écrêtage. En présence du canal bruité, l'écrêtage inversible a un gain sur le back-off du PA et donc sur son rendement. Ainsi le gain en consommation a été quantifié à 11% pour les mêmes performances en BER (Bit Error Rate). En outre, une analyse plus approfondie a été réalisée pour l'ACPR et un nouveau paramètre (le N_ACPR) permet de mieux prendre en compte la remontée spectrale des lobes secondaires du spectre de sortie.