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There is a crucial need for real time detection and diagnosis in digital mammography. To date, most computer aided analysis applications are software driven and normally require long processing times. Digital filtering is often the initial stage in processing mammograms for both automated detection and tissue characterization, which relies on Fourier analysis. In this research the main objective is to lay the groundwork for converting software driven mammography applications to hardware implementations by using Application-Specific Integrated Circuits (ASICs). The long-term goal is to increase processing speed. This research focuses on achieving the main objective by using one specific mammographic image processing application for demonstration purposes. ASICs offer high performance at the price of high development costs and are suitable for real time diagnosis. In this research, we develop a behavioral VHDL model of a specific filtering algorithm. Automatic Design Instantiation System (AUDI)8, a high level synthesis tool is used to automatically synthesize an RTL design from the model. A floating point behavioral component library is developed to support the synthesis of the filtering algorithm. The work shows that the hardware output is identical to the software driven output at when considering eight-bit accuracy and shows only rounding errors at higher storage capacities.

We present the high level (VHDL) modeling and high level synthesis of an ASIC (TOUR NAVIGATOR) for a portable hand held device - a tour guide. The tour guide is based on location-aware mobile computing, which gives the information of the current location to the user. The TOUR NAVIGATOR designed in this work is interfaced with off-the-shelf components to realise the tour guide system. The current location is given by an on-board GPS receiver chip. The TOUR NAVIGATOR is a search and play module which interfaces with the flash memory, GPS receiver and the audio codec. The functionality of the TOUR NAVIGATOR is to search the flash memory for audio data corresponding to the current GPS co-ordinate, which is an input to the TOUR NAVIGATOR. The look-up table containing the GPS coordinates and the corresponding audio files are loaded into the flash memory, where in each GPS entry in the table is indexed by the co-ordinates, and an audio file that contains information about the locations is associated with it. When there is a match, the audio file is streamed to the codec. The functionality of the interface of the TOUR NAVIGATOR with the memory module is verified at the RTL using Cadence-NCLaunch. The layout implementation of the TOUR NAVIGATOR is done using an automatic place and route tool (Silicon Ensemble), which uses standard cells for the entire design. Leakage power reduction is done by introducing sleep transistors in the standard cells. The TOUR NAVIGATOR is put into a "sleep" mode when there is no operation of the tour guide, thus giving significant power savings.

<p>In this thesis, an intuitive approach to determine scheduling and allocation of a behavioral algorithm defined by a netlist is presented. In this approach, scheduling is based on a weighted list scheduling where operations have the longest critical path are scheduled first. The component allocations are resorted to the PDCPA algorithm which focus on making efficient and correct clusters for hardware reuse problem. Several constraints are used in order to ensure the causality of processes and prevent conflicts of hardware components. This approach can give the total number of control steps and the number of registers and multiplexers in detail. Hence, designers obtain useful information from it and can make trade-offs between different resource conditions. </p><p>The program is implemented in MATLAB programming environment and provides parts of behavioral synthesis to facilitate the whole synthesis procedure.</p>

In this thesis, an intuitive approach to determine scheduling and allocation of a behavioral algorithm defined by a netlist is presented. In this approach, scheduling is based on a weighted list scheduling where operations have the longest critical path are scheduled first. The component allocations are resorted to the PDCPA algorithm which focus on making efficient and correct clusters for hardware reuse problem. Several constraints are used in order to ensure the causality of processes and prevent conflicts of hardware components. This approach can give the total number of control steps and the number of registers and multiplexers in detail. Hence, designers obtain useful information from it and can make trade-offs between different resource conditions. The program is implemented in MATLAB programming environment and provides parts of behavioral synthesis to facilitate the whole synthesis procedure.

Aggressive scaling of nanoscale CMOS integrated circuits has created significant design challenges arising from increasing power densities, thermal concerns, and rising wire delays. The main contribution of this dissertation is the development of unified physical and high-level synthesis techniques for the design of ASICs with optimal chip temperatures and interconnect delays. Thermal issues are becoming a serious problem in high-performance VLSI circuits, adversely impacting performance, reliability, power consumption, and cooling costs. To address this, we present a temperature-aware behavioral synthesis (TABS) framework that combines power minimization with temperature-aware task scheduling, resource binding, and floorplanning. Compared to conventional low-power synthesis methods, our approach is effective in synthesizing circuits with lower chip temperatures and more uniform thermal distributions, with temperature reductions up to 23% when compared to low-power synthesis. We propose three techniques to address interconnect delays during high-level synthesis: (1) a simulated annealing (SA) based layout-aware high-level synthesis technique for 3-D integrated circuits, that tightly couples the synthesis tasks of resource binding and 3-D floorplanning. The proposed algorithm significantly outperforms a conventional synthesis flow that separates the binding and floorplanning steps, with improvements in the total wirelength by 29% and of the longest wirelength by 21%; (2) a floorplan-aware high-level synthesis technique that uses the topology of multi-terminal nets to improve interconnect delay estimates during resource binding. Experiments show that the use of accurate wire delay estimates during binding can reduce wire delays by as much as 49% in 70nm technology; (3) an iterative high-level design-space exploration engine that uses a priori stochastic wirelength estimates to guide binding decisions during high-level synthesis. The proposed approach offers a significant speed-up during design space exploration when compared to approaches that use traditional place-and-route to evaluate candidate solutions. Finally, we present a genetic algorithm (GA) based approach for high-level synthesis. We propose novel GA encoding, crossover, and mutation operators for the problem. The quality of the results generated by the GA are superior to those of several other techniques reported in the literature.

Field Programmable Gate Arrays (FPGAs) are programmable logic devices used for the implementation of a wide range of digital systems. In recent years, there has been an increasing interest in design methodologies that allow high-level design descriptions to be automatically implemented in FPGAs. This thesis describes the design and implementation of a novel compilation flow that implements circuits in FPGAs from a streaming programming language. The streaming language supported is called FPGA Brook, and is based on the existing Brook and GPU Brook languages, which target streaming multiprocessors and graphics processing units (GPUs), respectively. A streaming language is suitable for targeting FPGAs because it allows system designers to express applications in a way that exposes parallelism, which can then be exploited through parallel hardware implementation. FPGA Brook supports replication, which allows the system designer to trade-off area for performance, by specifying the parts of an application that should be implemented as multiple hardware units operating in parallel, to achieve desired application throughput. Hardware units are interconnected through FIFO buffers, which effectively utilize the small memory modules available in FPGAs. The FPGA Brook design flow uses a source-to-source compiler, and combines it with a commercial behavioural synthesis tool to generate hardware. The source-to-source compiler was developed as a part of this thesis and includes novel algorithms for implementation of complex reductions in FPGAs. The design flow is fully automated and presents a user-interface similar to traditional software compilers. A suite of benchmark applications was developed in FPGA Brook and implemented using our design flow. Experimental results show that applications implemented using our flow achieve much higher throughput than the Nios II soft processor implemented in the same FPGA device. Comparison to the commercial C2H compiler from Altera shows that while simple applications can be effectively implemented using the C2H compiler, complex applications achieve significantly better throughput when implemented by our system. Performance of many applications implemented using our design flow would scale further if a larger FPGA device were used. The thesis demonstrates that using an automated design flow to implement streaming applications in FPGAs is a promising methodology.

Field Programmable Gate Arrays (FPGAs) are programmable logic devices used for the implementation of a wide range of digital systems. In recent years, there has been an increasing interest in design methodologies that allow high-level design descriptions to be automatically implemented in FPGAs. This thesis describes the design and implementation of a novel compilation flow that implements circuits in FPGAs from a streaming programming language. The streaming language supported is called FPGA Brook, and is based on the existing Brook and GPU Brook languages, which target streaming multiprocessors and graphics processing units (GPUs), respectively. A streaming language is suitable for targeting FPGAs because it allows system designers to express applications in a way that exposes parallelism, which can then be exploited through parallel hardware implementation. FPGA Brook supports replication, which allows the system designer to trade-off area for performance, by specifying the parts of an application that should be implemented as multiple hardware units operating in parallel, to achieve desired application throughput. Hardware units are interconnected through FIFO buffers, which effectively utilize the small memory modules available in FPGAs. The FPGA Brook design flow uses a source-to-source compiler, and combines it with a commercial behavioural synthesis tool to generate hardware. The source-to-source compiler was developed as a part of this thesis and includes novel algorithms for implementation of complex reductions in FPGAs. The design flow is fully automated and presents a user-interface similar to traditional software compilers. A suite of benchmark applications was developed in FPGA Brook and implemented using our design flow. Experimental results show that applications implemented using our flow achieve much higher throughput than the Nios II soft processor implemented in the same FPGA device. Comparison to the commercial C2H compiler from Altera shows that while simple applications can be effectively implemented using the C2H compiler, complex applications achieve significantly better throughput when implemented by our system. Performance of many applications implemented using our design flow would scale further if a larger FPGA device were used. The thesis demonstrates that using an automated design flow to implement streaming applications in FPGAs is a promising methodology.