The importance of a smooth user experience in applications is increasing. To achieve more performance when interacting with resource intensive data it is important to implement an efficient caching method. The goal of this thesis is to investigate how to implement an efficient cache in an Android application. The use case is to download metadata and images of movies from a WebAPI provided by June AB. In order to investigate which caching method is the most efficient, a pre-study was done on some of the most common caching methods today. Based on the results of the pre-study, two different caching algorithms were tested and evaluated: First-In First-Out (FIFO) and Least Recently Used (LRU). These two algorithms were then implemented in an Android application. The resulting prototype has a responsive user interface capable of caching large amounts of data without noticeable performance loss compared to a non-cached version. The results from the prototype showed that LRU is the better strategy in our use case, however what we discovered was that the buffer size of the cache has the biggest impact on performance, not the cache eviction strategy. / Vikten av en snabb användarupplevelse ökar i nya applikationer. För att få ut mer prestanda när användare interagerar med resurstung data är det viktigt att implementera en effektiv cachingsmetod. Målet med arbetet är att undersöka hur man implementerar en effektiv cache i en Android-applikation. Användarfallet är att ladda ner metadata och bilder på filmer från ett WebAPI som tillhandahölls av June AB. För att undersöka vilken cachingsmetod som är effektivast gjordes en förstudie på några av de mest vanliga cachingsmetoderna idag. Baserat på förstudiens resultat valdes två cachingsalgoritmer för testning och utvärdering: First-In First-Out (FIFO) och Least Recently Used (LRU). Dessa två algoritmer implementerades i en Android-applikation Prototypen som gjordes har ett responsivt användargränsnitt som kan cacha stora mängder data utan märkbar prestandaförlust jämfört med en icke-cachad version. Prototypen visade att LRU är den bättre strategin för vårt användarfall, men upptäckte att bufferstorleken på cachen har den största påverkan av prestandan, inte cachestrategin.

<p>NXP Semiconductors (formerly Philips Semiconductors) has created a new embedded asynchronous FIFO module. It is a small and fast full-custom design with Design-for-Test (DfT) functionality. The fault detection qualities of a proposed manufacturing test for this FIFO have been analyzed by a defect-based method based on analog simulation. Resistive bridges and opens of different sizes in the bit-cell matrix and in the asynchronous control have been investigated.</p><p>The fault coverage for bridge defects in the bit-cell matrix of the initial FIFO test has been improved by inclusion of an additional data background and low-voltage testing. 100% fault coverage is reached for low resistance bridges. The fault coverage for opens has been improved by a new test procedure including waiting periods.</p><p>98.4% of the hard bridge defects in the asynchronous control slices can be detected with some modifications of the initial test.</p>

NXP Semiconductors (formerly Philips Semiconductors) has created a new embedded asynchronous FIFO module. It is a small and fast full-custom design with Design-for-Test (DfT) functionality. The fault detection qualities of a proposed manufacturing test for this FIFO have been analyzed by a defect-based method based on analog simulation. Resistive bridges and opens of different sizes in the bit-cell matrix and in the asynchronous control have been investigated. The fault coverage for bridge defects in the bit-cell matrix of the initial FIFO test has been improved by inclusion of an additional data background and low-voltage testing. 100% fault coverage is reached for low resistance bridges. The fault coverage for opens has been improved by a new test procedure including waiting periods. 98.4% of the hard bridge defects in the asynchronous control slices can be detected with some modifications of the initial test.

<p>A design methodology to mitigate timing problems due to long wire delays is proposed. The timing problems are taking care of at architecture level instead of layout level in this design method so that no change is needed when the whole design goes to backend design. Hence design iterations are avoided by using this design methodology. The proposed design method is based on STARI architecture, and a novel initialization mechanism is proposed in this paper. Low frequency global clock is used to synchronize the communication and PLLs are used to provide high frequency working clocks. The feasibility of new design methodology is proved on FPGA test board and the implementation details are also described in this paper. Only standard library cells are used in this design method and no change is made to the traditional design flow. The new design methodology is expected to reduce the timing closure effort in high frequency and complex digital design in deep submicron technologies.</p>

In diesem Beitrag lesen Sie: • was unter innerbetrieblicher Logistik verstanden werden kann, • wie ERP- und PPS Systeme Funktionen der innerbetrieblichen Logistik erfüllen, • welche zukunftsorientierten Technologien durch diese Systeme unterstützt werden.

A design methodology to mitigate timing problems due to long wire delays is proposed. The timing problems are taking care of at architecture level instead of layout level in this design method so that no change is needed when the whole design goes to backend design. Hence design iterations are avoided by using this design methodology. The proposed design method is based on STARI architecture, and a novel initialization mechanism is proposed in this paper. Low frequency global clock is used to synchronize the communication and PLLs are used to provide high frequency working clocks. The feasibility of new design methodology is proved on FPGA test board and the implementation details are also described in this paper. Only standard library cells are used in this design method and no change is made to the traditional design flow. The new design methodology is expected to reduce the timing closure effort in high frequency and complex digital design in deep submicron technologies.

Three different chip design topics associated with their respective applications are proposed in this thesis. The first topic is the implementation of an FIFO memory design for 8-to-32 data exchange bus. An FIFO memory architecture is proposed to be utilized in data exchange between processing units which possess non-homogeneous bus widths. Neither arbiter logics nor modules are required in such a design to determine input sequences or output sequences. Hence, the delay is drastically shortened. The second topic is focused on the implementation of an analog front-end of digital cordless headset baseband controller. The integrated analog and digital interface IC provides an interface for analog and digital communication. It converts an analog signal into an 8-bit digital signal, which will be processed by the baseband controller. It also converts an 8-bit digital voice data into an analog voice signal. In addition, a built-in oscillator is included in the design, which provides a global clock signal. The third topic is to carry out an DC/DC converter with a built-in voltage detector. The converter can convert 1.5V input voltage to 2.7V output voltage. A portable system can use only one single battery to power on by this circuit. It also contains a voltage detector to indicate whether the output voltage meets the pre-determined level.

Integer multicommodity network flow (MCNF) models have applications in various areas like logistics, freight transportation, telecommunication and manufacturing. In this thesis we study an extension of the integer MCNF problem (MCNF-FIFO) where commodities are handled (processed) in a first-in-first-out (FIFO) order at each transshipment location and resource capacities are shared across arcs in the network. The objective of the MCNF-FIFO model is to find feasible routes for all commodities from their origins to destinations while minimizing the total transportation and holding cost or the sum of delivery times. We formulate the MCNF-FIFO problem on a time-space network and develop three different integer-programming (IP) formulations for the FIFO constraints, and two IP formulations for the flow conservations requirements. Since these formulations have a very large number of variables and constraints, we develop various algorithmic strategies to obtain good quality solutions quickly. The first strategy is to reduce the problem size by using properties of the optimal solution. We develop novel problem reduction and decomposition techniques that eliminate variables and constraints, and decompose the problem into smaller components. To further reduce the problem size, we classify the FIFO constraints into different categories by utilizing the relationships between different commodities, and provide specialized formulations for each of these categories so as to reduce the number of FIFO constraints significantly. The second strategy is to develop heuristic algorithms that provide near-optimal solutions to the MCNF-FIFO problem. Our first algorithm is an optimization-based heuristic that solves a relaxed MCNF-FIFO model with a limited number of FIFO constraints. Then, it removes the remaining infeasibilities in the solution of the relaxed MCNF-FIFO model using a repair heuristic to obtain a feasible solution. We develop two other heuristic algorithms that are stand-alone construction heuristics that build a feasible solution from scratch. To assess the effectiveness of the modeling and algorithmic enhancements, we implement the methods and apply them to three real life test instances. Our tests show that the problem reduction techniques are very effective in reducing the solution times. Among the heuristic algorithms, the optimization-based heuristic performs the best to find near-optimal solutions quickly. / text

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<p>Vid implementeringar av FIFO-arkitekturer har asynkrona FIFO-konstruktioner använts. Denna lösningsmetod har visat sig innehålla en del brister vid tillämpning på höghastighets system, vilket ledde till att synkrona FIFOn började ersätta asynkrona FIFOn. </p><p>Den synkrona arkitekturen har samma funktonalitet som de asynkrona typerna med fördelar som högre hastighet och enklare gränssnitt. </p><p>I rapporten har olika FIFO-konstruktioner behandlats och jämförelser har gjorts mellan synkrona och asynkrona arkitekturer. Det vid ISY konstruerade SRAM-minnet har sedan avgjort vilken typ av FIFO-arkitektur som varit bäst lämpad för implementering. </p><p>Det implementerade FIFO-minnet ordnar indata- och utdataflöden till ett enkelports SRAM-minne på 256 ord med 16 bitar per ord.</p> / <p>Previous implementations of FIFO-architectures has often been asynchronous FIFO-constructions. This method has some limitations in high speed systems. Instead synchronous FIFOs has more and more replaced asynchronous FIFOs. </p><p>The synchronous architecture has the same features as the asynchronous but with advantages such as higher speed and simplified interface. </p><p>In the report different types of FIFO-constructions has been studied and comparison between synchronous and asynchronous architectures has been done. The memory unit developed by ISY decided which FIFO-architecture that were best suited for the implementation. </p><p>The implemented FIFO-memory arrange in- and outdataflow to a single-port SRAM memory containing 256 words with 16 bits per word.</p>