This article describes an inexpensive way of clock generation for FPGA-based circuit cores, which reduces the number of external clock sources and eases synchronization problems. We introduce a modified version of the BRESENHAM line drawing algorithm and use it outside its original application domain for the rational division of clocks. An optimized hardware design for BRESENHAM-based clock division is presented and the quality of its output is evaluated. The optimal initialization conditions in terms of phase shift and jitter are identified and formally proven. Finally, the complexity characteristics of a generic synthesizable VHDL design based on this algorithm are examined and verified by synthesis examples. Special attention is paid to implementation results in conjunction with different FPGA families.

This article describes an inexpensive way of clock generation for FPGA-based circuit cores, which reduces the number of external clock sources and eases synchronization problems. We introduce a modified version of the BRESENHAM line drawing algorithm and use it outside its original application domain for the rational division of clocks. An optimized hardware design for BRESENHAM-based clock division is presented and the quality of its output is evaluated. The optimal initialization conditions in terms of phase shift and jitter are identified and formally proven. Finally, the complexity characteristics of a generic synthesizable VHDL design based on this algorithm are examined and verified by synthesis examples. Special attention is paid to implementation results in conjunction with different FPGA families.

<p>This paper describes our game engine written in C++, using the DirectX libraries for graphics, sound and input. Since the engine is written using DirectX, an introduction to this system is given. The report gives a description of the structure of the game and the game kernel. Following this is a description of the graphics engine and its core components. The main focus of the engine is on the physics and how it is used in the game to simulate reality. Input is discussed briefly, with examples to show how it relates to the physics engine. Implementation of audio in the game engine is not described, but a general description of how sound is used in games is given. A theory for the basics of how artificial intelligence can be used in the engine is presented. The system for the architecture of the levels is described as is its connection to the graphics engine. The last section of the report is an evaluation and suggestions for what to do in the future. A user manual for the level editor is included as an appendix.</p>

This paper describes our game engine written in C++, using the DirectX libraries for graphics, sound and input. Since the engine is written using DirectX, an introduction to this system is given. The report gives a description of the structure of the game and the game kernel. Following this is a description of the graphics engine and its core components. The main focus of the engine is on the physics and how it is used in the game to simulate reality. Input is discussed briefly, with examples to show how it relates to the physics engine. Implementation of audio in the game engine is not described, but a general description of how sound is used in games is given. A theory for the basics of how artificial intelligence can be used in the engine is presented. The system for the architecture of the levels is described as is its connection to the graphics engine. The last section of the report is an evaluation and suggestions for what to do in the future. A user manual for the level editor is included as an appendix.

This thesis presents a comparison between different algorithms for optimal scanline voxelization of 3D models.As the optimal scanline relies on line voxelization, three such algorithms were evaluated. These were Real Line Voxelization (RLV), Integer Line Voxelization (ILV) and a 3D Bresenham line drawing algorithm. RLV and ILV were both based on voxel traversal by Amanatides and Woo. The algorithms were evaluated based on runtime and the approximation error of the integer versions, ILV and Bresenham. The result was that RLV performed better in every case, with ILV being 20-250% slower and Bresenham being 20-500% slower. The error metric used was the Jaccard distance and generally started at 20% and grew up towards 25% for higher voxel resolutions. This was true for both ILV and Bresenham. The conclusion was that there is no reason to use any of the integer versions over RLV. As they both performed and approximated the original 3D model worse.

It was previously shown that the BRESENHAM algorithm is well-suited for digital fractional clock generation. Specifically, it proved to be the optimal approximation of a desired clock in terms of the switching edges provided by an available reference clock. Moreover, some synthesis results for hardwired dividers on Altera FPGAs showed that this technique for clock division achieves a high performance often at or close to the maximum frequency supported by the devices for moderate bit widths of up to 16 bits. This paper extends the investigations on the clock division by the BRESENHAM algorithm. It draws out the limits encountered by the existing implementation for both FPGA and VLSI realizations. A rather unconventional adoption of the carry-save representation combined with a soft-threshold comparison is proposed to circumvent these limitations. The resulting design is described and evaluated. Mathematically appealing results on the quality of the approximation achieved by this approach are presented. The underlying proofs and technical details are provided in the appendix.

The objective of this thesis is creating interface for the picture generator. The interface generates a VGA signal with possibility of 4bit color depth. The interface controls two chips of one port SRAM IS61 witch is supplied with Digilent Spartan-3 Starter Kit Board and comunicates trought FIFO blocks based on the shift register principle. Graphics interface generates lines and secondary forms, circles and secondary forms, fills area up and controles 2D transformations of picture.

It was previously shown that the BRESENHAM algorithm is well-suited for digital fractional clock generation. Specifically, it proved to be the optimal approximation of a desired clock in terms of the switching edges provided by an available reference clock. Moreover, some synthesis results for hardwired dividers on Altera FPGAs showed that this technique for clock division achieves a high performance often at or close to the maximum frequency supported by the devices for moderate bit widths of up to 16 bits. This paper extends the investigations on the clock division by the BRESENHAM algorithm. It draws out the limits encountered by the existing implementation for both FPGA and VLSI realizations. A rather unconventional adoption of the carry-save representation combined with a soft-threshold comparison is proposed to circumvent these limitations. The resulting design is described and evaluated. Mathematically appealing results on the quality of the approximation achieved by this approach are presented. The underlying proofs and technical details are provided in the appendix.

Diplomová práce je zaměřena na metody zobrazování skalárních dat v pevné datové mřížce, konkrétně dat získaných užitím fluorescenčního konfokálního mikroskopu. Teoretická část textu začíná představením fungování konfokálních mikroskopů a zasazení problematiky zkoumaných grafických metod do matematického kontextu. Následující kapitola se věnuje odvození integrálu pro zobrazování objemů a z něj vyplývající back-to-front metodu. Teoretická část je zakončena představením metod vhodných pro zobrazování trojrozměrných skalárních dat při použití back-to-front algoritmu. V praktické části je pak popsán implementovaný algoritmus.

In this master’s thesis we focus on the basic properties of computer curves and their practical applicability. We explain how the curve can be understood in general, what are polynomial curves and their composing possibilities. Then we focus on the description of Bezier curves, especially the Bezier cubic. We discuss in more detail some of fundamental algorithms that are used for modelling these curves on computers and then we will show their practical interpretation. Then we explain non uniform rational B-spline curves and De Boor algorithm. In the end we discuss topic rasterization of segment, thick line, circle and ellipse. The aim of master’s thesis is the creation of the set of interactive applets, simulating some of the methods and algorithm we discussed in theoretical part. This applets will help facilitate understanding and will make the teaching more effective.