This research aims to discuss the integration of an 10/100 Ethernet MAC on a System-on-a-Programmble-Chip. SOPC is a chip combined with ¡§ASIC¡¨(Application Specific IC) and ¡§PLD¡¨(Programmable Logic Device). Due to the lower Complexity, SOPC is suitable for SOC study in academic. In this research, Altera ARM-based ExcaliburTM SOPC is used and an Opencore 10/100 Ethernet MAC is integrated onto it. The topic of SOPC architecture, SOPC development flow, bus interface design of the hardware, driver development and verification strategy of SOPC are discussed. This work is hopeful to be referable material for school SOPC teaching.

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Asynchronous bus interface units to AMBA AHB are designed so that an OpenGL ES 2.0 vertex shader can communicate with other hardware units via AHB bus under different working frequencies. The first design is to directly implement an asynchronous AHB wrapper for the vertex shader. The other two designs are based on Open Core Protocol (OCP) to allow for more flexibility. The hardware intellectual property (IP), vertex shader in this thesis, to OCP asynchronous unit is designed so that the IP can be developed independently with different bus protocols as long as the OCP-to-bus interface is provided for a particular bus protocol. With the help of asynchronous IP-to-OCP and OCP-to-AHB interface units, the vertex shader IP can operate at different frequencies from the AHB bus. Furthermore, the same vertex shader (VS) can be connected to other bus protocol (such as AXI) of different frequencies if the OCP-to-AXI interface is provided because the the asynchronous VS-to-OCP have been designed in this thesis.

The master thesis deals with analysis of existing solutions and architecture design of new solutions for management of unix-like systems. The resulting system is usable for configuration of the local system over the D-Bus and remotely over the network. Usability for cloud computing has been considered during design.