[No abstract available] / Applied Science, Faculty of / Electrical and Computer Engineering, Department of / Graduate

ABSTRACT This thesis presents the equivalent circuit of basic semicondonductor equations, which are implemented as the device elements of circuit simulator: spice3. We use a simple example of a pn junction diode to study the DC and transient characteristics. Using this technique, it is easy to simulate the semiconductor device composed of the elements and to include the semiconductor device as a part of a circuit.

In this thesis, a switched-current sample-and-hold circuit is proposed. We use feedback circuit to decrease the input impedance and to reduce the transmission error in SI cell. Furthermore, the entire memory cell is designed in a coupled differential replicate form to eliminate the clock feedthrough (CFT) error. The sample-and-hold circuit is simulated using the parameters of TSMC 0.35£gm CMOS process. The simulation results show that the spurious-free dynamic range (SFDR) is 55 dB, the sampling rate is 40MHz, the power consumption is 0.38 mW, and the power supply is 1.5V. Furthermore, the circuit is verified by cadence-hspice simulation.

No description available.

La photonique Josephson est un domaine récent de la physique à la croisée entre l’électrodynamique quantique en circuit et le blocage de Coulomb dynamique. Elle explique et étudie la possibilité pour une paire de Cooper de traverser une jonction Josephson polarisée en tension par effet tunnel inélastique, en dissipant la différence de potentiel électrique aux bornes de la jonction sous forme de photons émis dans l’environnement électromagnétique de la jonction.Cette thèse s’arrête sur deux aspects de la photonique Josephson:• La possibilité de contrôler la statistique des photons émis dans l’environnement, en particulier Générer des photons non-classiques;• La possibilité de stimuler l’émission de photons, ce qui permet d’Amplifier avec un bruit ajouté à la limite quantique.Pour fonctionner ces dispositifs ne demandent qu’une simple tension continue servant à polariser la jonction Josephson. A terme ces dispositifs pourraient simplifier certaines mesures quantiques en remplaçant avantageusement des dispositifs micro-ondes existants plus difficiles à utiliser.Nous avons étudié nos dispositifs avec deux théories, la théorie P(E) et celle liant les flux de photons entrant et sortant, pour en tirer les caractéristiques de fonctionnement de nos dispositifs : taux d’émission, gain, bruit, bande passante, point de compression. Les dispositifs expérimentaux mesurés sont réalisés en nitrure de niobium en créant un environnement électromagnétique répondant à nos besoins. La possibilité de contrôler les processus photoniques que l’on veut en réalisant l’environnement électromagnétique adapté laisse la porte ouverte à de futures dispositifs : divers sources non-classiques, amplificateurs large bande, détecteurs de photons. / The recent field of Josephson photonics is about the interplay between circuit quantum electrodynamic and dynamical Coulomb blockade. It explains and studies the ability of a Cooper pair to inelasticity tunnel through a DC-biased Josephson junction by dissipating the Cooper pair energy in the electromagnetic environment of the junction in the form of photons.This thesis focuses on two aspects of the Josephson photonics:• Control over the statistics of the emitted photons with focus on Generation of non-classical photons;• Stimulated emission of photons leading to Amplification with added noise at the quantumlimit.These devices are powered with a simple DC voltage used to biased the Josephson junction. Such devices can be a new solution in a frequencies range where only few simple alternative solutions are now available.We have studied our devices with two theories, P-theory and input output theory, to derive working characteristics of our devices : Photon rate, gain, noise, bandwidth, compression point. The measured samples are made of niobium nitride and the electromagnetic environment of the junction is engineered to fulfil our needs. The possibility to select the photonic processes at will by engineering the electromagnetic environment permits to imagine further devices: other types of sources, wideband amplifiers, photon detectors.

Architectural research for Field-Programmable Gate Arrays (FPGAs) tends to use an experimental approach. The benchmark circuits are used not only to compare different architectures, but also to ensure that the FPGA is sufficiently flexible to implement the desired variety of circuits. The most common benchmark circuits used for architectural research are circuits from the Microelectronics Center of North Carolina (MCNC). These circuits are small; they occupy less than 3% [5] of the largest available commercial FPGA. Moreover, these circuits are more representative of the glue logic circuits that were targets of early devices. This contrasts with the trend towards implementing Systems on Chip (SoCs) on FPGAs where several functional modules are integrated into a single circuit which is mapped onto one device. In this thesis, we develop a synthetic system-level circuit generator that connects pre-existing circuits in a realistic manner to build large netlists that share the characteristics of real SoC circuits. This generator is based on a survey of contemporary circuit designs from industrial and academic sources. We demonstrate that these system-level circuits scale well and that their post-routing characteristics match the results of large pre-existing benchmarks better than the results of circuits from previous synthetic generators.

The prevalence of multi-core processors in recent years has introduced new opportunities and challenges to Electronic Design Automation (EDA) research and development. In this dissertation, a few parallel Very Large Scale Integration (VLSI) circuit analysis and optimization methods which utilize the multi-core computing platform to tackle some of the most difficult contemporary Computer-Aided Design (CAD) problems are presented. The first CAD application that is addressed in this dissertation is analyzing and optimizing mesh-based clock distribution network. Mesh-based clock distribution network (also known as clock mesh) is used in high-performance microprocessor designs as a reliable way of distributing clock signals to the entire chip. The second CAD application addressed in this dissertation is the Simulation Program with Integrated Circuit Emphasis (SPICE) like circuit simulation. SPICE simulation is often regarded as the bottleneck of the design flow. Recently, parallel circuit simulation has attracted a lot of attention. The first part of the dissertation discusses circuit analysis techniques. First, a combination of clock network specific model order reduction algorithm and a port sliding scheme is presented to tackle the challenges in analyzing large clock meshes with a large number of clock drivers. Our techniques run much faster than the standard SPICE simulation and existing model order reduction techniques. They also provide a basis for the clock mesh optimization. Then, a hierarchical multi-algorithm parallel circuit simulation (HMAPS) framework is presented as an novel technique of parallel circuit simulation. The inter-algorithm parallelism approach in HMAPS is completely different from the existing intra-algorithm parallel circuit simulation techniques and achieves superlinear speedup in practice. The second part of the dissertation talks about parallel circuit optimization. A modified asynchronous parallel pattern search (APPS) based method which utilizes the efficient clock mesh simulation techniques for the clock driver size optimization problem is presented. Our modified APPS method runs much faster than a continuous optimization method and effectively reduces the clock skew for all test circuits. The third part of the dissertation describes parallel performance modeling and optimization of the HMAPS framework. The performance models and runtime optimization scheme improve the speed of HMAPS further more. The dynamically adapted HMAPS becomes a complete solution for parallel circuit simulation.

Because of the unique architecture of wireless receivers, a designer must understand both the high frequency aspects as well as the low-frequency analog considerations for different building blocks of the receiver. The primary goal of this research work is to explore techniques for implementing high performance RF and baseband building blocks for wireless applications. Several novel techniques to improve the performance of analog building blocks are presented. An enhanced technique to couple two LC resonators is presented which does not degrade the loaded quality factor of the resonators which results in an increased dynamic range. A novel technique to automatically tune the quality factor of LC resonators is presented. The proposed scheme is stable and fast and allows programming both the quality factor and amplitude response of the LC filter. To keep the oscillation amplitude of LC VCOs constant and thus achieving a minimum phase noise and a reliable startup, a stable amplitude control loop is presented. The proposed scheme has been also used in a master-slave quality factor tuning of LC filters. An efficient and low-cost architecture for a 3.1GHz-10.6GHz ultra-wide band frequency synthesizer is presented. The proposed scheme is capable of generating 14A novel pseudo-differential transconductance amplifier is presented. The proposed scheme takes advantage of the second-order harmonic available at the output current of pseudo-differential structure to cancel the third-order harmonic distortion. A novel nonlinear function is proposed which inherently removes the third and the fifth order harmonics at its output signal. The proposed nonlinear block is used in a bandpass-based oscillator to generate a highly linear sinusoidal output. Finally, a linearized BiCMOS transconductance amplifier is presented. This transconductance is used to build a third-order linear phase low pass filter with a cut-off frequency of 264MHz for an ultra-wide band receiver. carrier frequencies.

Architectural research for Field-Programmable Gate Arrays (FPGAs) tends to use an experimental approach. The benchmark circuits are used not only to compare different architectures, but also to ensure that the FPGA is sufficiently flexible to implement the desired variety of circuits. The most common benchmark circuits used for architectural research are circuits from the Microelectronics Center of North Carolina (MCNC). These circuits are small; they occupy less than 3% [5] of the largest available commercial FPGA. Moreover, these circuits are more representative of the glue logic circuits that were targets of early devices. This contrasts with the trend towards implementing Systems on Chip (SoCs) on FPGAs where several functional modules are integrated into a single circuit which is mapped onto one device. In this thesis, we develop a synthetic system-level circuit generator that connects pre-existing circuits in a realistic manner to build large netlists that share the characteristics of real SoC circuits. This generator is based on a survey of contemporary circuit designs from industrial and academic sources. We demonstrate that these system-level circuits scale well and that their post-routing characteristics match the results of large pre-existing benchmarks better than the results of circuits from previous synthetic generators.

Architectural research for Field-Programmable Gate Arrays (FPGAs) tends to use an experimental approach. The benchmark circuits are used not only to compare different architectures, but also to ensure that the FPGA is sufficiently flexible to implement the desired variety of circuits. The most common benchmark circuits used for architectural research are circuits from the Microelectronics Center of North Carolina (MCNC). These circuits are small; they occupy less than 3% [5] of the largest available commercial FPGA. Moreover, these circuits are more representative of the glue logic circuits that were targets of early devices. This contrasts with the trend towards implementing Systems on Chip (SoCs) on FPGAs where several functional modules are integrated into a single circuit which is mapped onto one device. In this thesis, we develop a synthetic system-level circuit generator that connects pre-existing circuits in a realistic manner to build large netlists that share the characteristics of real SoC circuits. This generator is based on a survey of contemporary circuit designs from industrial and academic sources. We demonstrate that these system-level circuits scale well and that their post-routing characteristics match the results of large pre-existing benchmarks better than the results of circuits from previous synthetic generators. / Applied Science, Faculty of / Electrical and Computer Engineering, Department of / Graduate