The facility to capture the arrival of a single photon, is the fundamental limit to the detection of quantised electromagnetic radiation. An image sensor capable of capturing a picture with this ultimate optical and temporal precision is the pinnacle of photo-sensing. The creation of high spatial resolution, single photon sensitive, and time-resolved image sensors in complementary metal oxide semiconductor (CMOS) technology offers numerous benefits in a wide field of applications. These CMOS devices will be suitable to replace high sensitivity charge-coupled device (CCD) technology (electron-multiplied or electron bombarded) with significantly lower cost and comparable performance in low light or high speed scenarios. For example, with temporal resolution in the order of nano and picoseconds, detailed three-dimensional (3D) pictures can be formed by measuring the time of flight (TOF) of a light pulse. High frame rate imaging of single photons can yield new capabilities in super-resolution microscopy. Also, the imaging of quantum effects such as the entanglement of photons may be realised. The goal of this research project is the development of such an image sensor by exploiting single photon avalanche diodes (SPAD) in advanced imaging-specific 130nm front side illuminated (FSI) CMOS technology. SPADs have three key combined advantages over other imaging technologies: single photon sensitivity, picosecond temporal resolution and the facility to be integrated in standard CMOS technology. Analogue techniques are employed to create an efficient and compact imager that is scalable to mega-pixel arrays. A SPAD-based image sensor is described with 320 by 240 pixels at a pitch of 8μm and an optical efficiency or fill-factor of 26.8%. Each pixel comprises a SPAD with a hybrid analogue counting and memory circuit that makes novel use of a low-power charge transfer amplifier. Global shutter single photon counting images are captured. These exhibit photon shot noise limited statistics with unprecedented low input-referred noise at an equivalent of 0.06 electrons. The CMOS image sensor (CIS) trends of shrinking pixels, increasing array sizes, decreasing read noise, fast readout and oversampled image formation are projected towards the formation of binary single photon imagers or quanta image sensors (QIS). In a binary digital image capture mode, the image sensor offers a look-ahead to the properties and performance of future QISs with 20,000 binary frames per second readout with a bit error rate of 1.7 x 10-3. The bit density, or cumulative binary intensity, against exposure performance of this image sensor is in the shape of the famous Hurter and Driffield densitometry curves of photographic film. Oversampled time-gated binary image capture is demonstrated, capturing 3D TOF images with 3.8cm precision in a 60cm range.

abstract: The market for high speed camera chips, or image sensors, has experienced rapid growth over the past decades owing to its broad application space in security, biomedical equipment, and mobile devices. CMOS (complementary metal-oxide-semiconductor) technology has significantly improved the performance of the high speed camera chip by enabling the monolithic integration of pixel circuits and on-chip analog-to-digital conversion. However, for low light intensity applications, many CMOS image sensors have a sub-optimum dynamic range, particularly in high speed operation. Thus the requirements for a sensor to have a high frame rate and high fill factor is attracting more attention. Another drawback for the high speed camera chip is its high power demands due to its high operating frequency. Therefore, a CMOS image sensor with high frame rate, high fill factor, high voltage range and low power is difficult to realize. This thesis presents the design of pixel circuit, the pixel array and column readout chain for a high speed camera chip. An integrated PN (positive-negative) junction photodiode and an accompanying ten transistor pixel circuit are implemented using a 0.18 µm CMOS technology. Multiple methods are applied to minimize the subthreshold currents, which is critical for low light detection. A layout sharing technique is used to increase the fill factor to 64.63%. Four programmable gain amplifiers (PGAs) and 10-bit pipeline analog-to-digital converters (ADCs) are added to complete on-chip analog to digital conversion. The simulation results of extracted circuit indicate ENOB (effective number of bits) is greater than 8 bits with FoM (figures of merit) =0.789. The minimum detectable voltage level is determined to be 470μV based on noise analysis. The total power consumption of PGA and ADC is 8.2mW for each conversion. The whole camera chip reaches 10508 frames per second (fps) at full resolution with 3.1mm x 3.4mm area. / Dissertation/Thesis / Masters Thesis Electrical Engineering 2017

Cell detection using image sensors is a novel and promising technique that can be used for diagnostic applications in medicine. For this purpose, cell detection studies with shadowing method are performed with yeast cells (Saccharomyces cerevisiae) using an 32&times / 32 complementary metal oxide semiconductor (CMOS) image sensor that is sensitive to optical illumination. Cells that are placed zero distance from the sensor surface are detected using the image sensor which is illuminated with four fixed leds to maintain fixed illumination levels in each test. Cells are transferred to the sensor surface with drying the medium they are in, which is phosphate buffered saline (PBS) solution. Yeast cells that are zero distance from the surface are detected with a detection rate of 72%. Then, MCF-7 (breast cancer) cells are detected with the same sensor when the PBS solution is about to dry. To investigate the detection capability of the sensor while the cells are in the PBS solution, the sensor surface is coated with gold in order to immobilize the surface with antibodies. With immobilizing antibodies, cells are thought to be bound to the surface achieving zero distance to the sensor surface. After coating gold, antibodies are immobilized, and same tests are done with MCF-7 cells. In the PBS solution, no sufficient results are obtained with the shadowing technique, but sufficient results are obtained when the solution is about to dry. After achieving cell detection with the image sensor, a similar but large format image sensor is designed. The designed CMOS image sensor has 160&times / 128 pixel array with 15&micro / m pitch. The pixel readout allows capacitive and optical detection. Thus, both DNA and cell detection are possible with this image sensor. The rolling line shutter mode is added for reducing further leakage at pixel readout. Addressing can be done which means specific array points can be investigated, and also array format can be changed for different size cells. The frame rate of the sensor can be adjusted allowing the detection of the fast moving cell samples. All the digital inputs of the sensor can be adjusted manually for the sake of flexibility. A large number of cells can be detected with using this image sensor due to its large format.

The theoretical and experimental investigation of the novel in-line CMOS image sensor was performed. This sensor is aimed to investigate particle size distribution, particle concentration and shape in hydraulic liquid in order to implement the proactive maintenance of hydraulic equipment. The existing instruments such as automatic particle counters and techniques are not sufficiently enough to address this task because of their restricted sensitivity, limit of concentration to be measured and they cannot determine particle shape. Other instruments cannot be used as inline sensors because they are not resistant to the arduous conditions such as high pressure and vibration. The novel mathematical model was proposed as it is not possible to use previously developed techniques based on using optical system and complicated algorithms. This model gives the output signal of the image sensor depending on the particle size, its distance from the light source (LED) and image sensor. Additionally, the model takes into account the limited exposure time and particle track simulation. The results of simulation based on the model are also performed in thesis. On the basis of the mathematical model the image processing algorithms were suggested in order to determine particle size even when this size is lower than pixel size. There are different approaches depending on the relation between the size of the particle and the pixel size. The approach to the volume of liquid sample estimation was suggested in order to address the problem of low accuracy of concentration measurement by the conventional automatic particle counters based on the single photodiode. Proposed technique makes corrections on the basis of particle velocity estimation. Approach to the accuracy estimation of the sensor was proposed and simulation results are shown. Generally, the accuracy of particle size and concentration measurement was considered. Ultimately, the experimental setup was used in order to test suggested techniques. The mathematical model was tested and the results showed sufficient correlation with the experiment. The zinc dust was used as a reference object as there are the particles within the range from 1 to 25 microns which is appropriate to check the sensitivity. The results of experiments using reference instrument showed the improved sensitivity and accuracy of volume measured compared to the reference one.

The objective of this research was to build a reprogrammable computational imager utilizing on-chip analog computations for the purpose of studying the capabilities of integrated sensing and processing. Unlike conventional imaging systems, which acquire image data and perform calculations on it, this system tightly integrates the computation and sensing into one process. This allows the exploration of intelligent and efficient sensory and processing. The IC architecture and circuit designs have focused on wide dynamic range signals. The fundamental computation performed is a separable two-dimensional transform. This allows various operations, including block transformations and separable convolutions. The operations are reprogramable and utilize analog memory and processing along with digital control. The random access to both the image plane and the computational operations allows for intraframe transform variations creating a hardware foundation for dynamic sampling and computation. One can also capture scenes with non-uniform resolution. Advantages, including utilization of feedback from processing to sensing and extensions of the technology including support for wavelets and larger transforms are also explored.

Pas de résumé / CMOS image sensor based on Active pixel sensor has considerably contributed to the imaging market and research interest in the past decade. Furthermore technology advancement has provided the capability to integrate more and more functionality into a single chip in multiple layers leading to a new paradigm, 3D integration. CMOS image sensor is one such application which could utilize the capability of 3D stacked architecture to achieve dedicated technologies in different layers, wire length reduction, less area, improved performancesThis research work is focused mainly on the early stages of design space exploration using hierarchical approach and aims at reducing time to market. This work investigates the imager from the top-down design perspective. Methodical anal y sis of imager is performed to achieve high level of flexibility and modularity. Re-useable models are developed to explore early design choices throughout the hierarchy. Finally, pareto front (providing trade off solutions) methodology is applied to explore the operating range of individual block at system level to help the designer making his design choice. Furthermore the thermal issues which get aggravated in the 3D stacked chip on the performance of the imager are studied. Systeme based thermal model is built to investigate the behavior of imager pixel matrix and to simulate the pixel matrix at high speed with acceptable accuracy compared to electrical simulations. The modular nature of the model makes simulations with future matrix extension straightforward. Validation of the thermal model with respect to electrical simulations is discussed. Finally an integrated design flow is developed to perform 3D floorplanning and to perform thermal anal y sis of the imager pixel matrix.

L'avancement de la technologie durant ces dernières années a permis aux imageurs d'atteindre de très hautes résolutions. Ceci a rendu les images plus riches en détails. D'un autre côté, une autre limitation se présente à ce niveau; celle du nombre de bits limité après la conversion analogique numérique. De ce fait, la qualité de l'image peut être affectée. Pour remédier à cette limitation et garder une meilleure qualité de l'image en sortie de son système d'acquisition, l'information lumineuse doit être codée sur un grand nombre de bits et conservée durant tout le flot de traitement pour éviter l'intervention du bruit et la génération des artefacts en sortie du système. En outre, le traitement numérique de chaque pixel sera coûteux en consommation d'énergie et en occupation de surface silicium.Le travail effectué dans cette thèse consiste à étudier, concevoir et implémenter plusieurs fonctions et architectures de traitement d'image en électronique analogique ou mixte. L'implémentation de ces fonctions en analogique permet de décaler la conversion de l'information lumineuse en numérique vers une étape ultérieure. ceci permet de conserver un maximum de précision sur l'information traitée. Ces fonctions et leurs architectures ont un but d'améliorer la dynamique de fonctionnement des imageurs CMOS standard (à intégration), en utilisant des techniques à temps d'intégration variable, et des "tone mapping" locaux qui imitent le système de vision humaine.Les principes de fonctionnement, les émulations sous MATLAB, la conception et les simulations électriques ainsi que les résultats expérimentaux des techniques proposées sont présentés en détails dans ce manuscrit. / The technology progress in recent years has enabled imagers to reach a very high resolutions. This allows images to be more detailed and rich in information. On the other hand, the limited number of bites after the digital analogue conversion may drastically affect the quality of the image. To maintain the quality of the output image of the acquisition system, the luminous information should be (1) encoded on a large number of bits and (2) maintained throughout the processing flow so that to avoid noise interference and generating artifacts system output. However, the digital processing of each pixel will be energy consuming will occupy more surface silicon.The goal of this thesis is to study, design and implement several image processing functions as well as their architectures using analog and mixed electronic. Implementation of these functions shifts the analog to digital conversion to a subsequent step. This allows a maximum precision of the processed information. The proposed functions and their architectures improve the operational dynamics Standard CMOS imagers using (1) variable integration time techniques, and (2) "tone mapping" which mimics the human vision system.The experimental results based on emulations in Matlab and the electrical design show the novelty and the efficiency of the proposed method.

京都大学 / 0048 / 新制・課程博士 / 博士(工学) / 甲第22442号 / 工博第4703号 / 新制||工||1734(附属図書館) / 京都大学大学院工学研究科原子核工学専攻 / (主査)教授 斉藤 学, 教授 神野 郁夫, 准教授 松尾 二郎 / 学位規則第4条第1項該当 / Doctor of Philosophy (Engineering) / Kyoto University / DFAM

<p>The introduction of the digital image sensor has triggered a revolution in the field of imaging. It has not only just replaced the conventional silver halide film based imaging system, but has also enormously widened the scope of imaging applications. Previously, charge-coupled devices (CCDs) were the most popular technology for image sensors. But in the past decade, they have been rapidly replaced by the CMOS image sensor (CIS) technology. The CCD image sensors offers higher sensitivity, wider dynamic range and better resolution compared to its CMOS imager counterparts. However, the lower power performance, higher speed of operation, easier integration with signal control and processing circuitries, and the use well-established mainstream fabrication process of CMOS technology, are key advantages that have served to propel CMOS imagers beyond CCDs in the market.</p> <p>However, CIS suffers from higher temporal noise compared to that of CCDs. One of the major noise sources in CIS is the 1/ noise generated from the in-pixel active amplifier. Due to continuous shrinking of MOS devices, the random telegraph signal (RTS) noise is emerging as a dominant noise source over other low frequency noise in CMOS imagers, resulting into reduced imaging performance.</p> <p>The RTS noise which evolves from trapping and de-trapping of electrons by the defects in the oxide, causes fluctuation in the drain current of the MOSFET. In this work, we have carried out time-domain measurement of RTS noise in CIS pixels. The time domain RTS measurements provide useful information about its characteristics in different operating conditions, which can be further used to extract the trap parameters and determine the optimum settings of operation of CIS.</p> <p>The capability of integrating various on-chip operations, higher speed and lower fabrication cost has made the CIS a good choice for various imaging applications. In order to demonstrate the extent of possible applications of CIS, we have developed an imaging system using a CIS. Two major concerns of biomedical imaging systems are their speed and cost. The system presented here is implemented using a CIS and FPGA (field programmable gate array) that provides a low-cost and high frame rate solution for biomedical microscopy.</p> / Master of Applied Science (MASc)

Color image acquisition and image processing have become a key in modern data application. In order to provide high quality images, the field of accurate acquisition is most important in respect to all further processing steps. But a whole variety of current image sensors possess incorrect color rendition due to insufficient accuracy of optical sensor parameters. This is detrimental especially for color sensors, because in these cases specific color information will be incorrectly acquired. Further, traditional color correction methods do not use information on the specific sensor spectral sensitivity, thus losing substantial information for color correction. The problem is investigated by introducing an algorithmic correction method which is capable of correcting dysfunctional sensor properties. The correction method is based on an enhancement of the CIE color perception model. According to this, color perception is modelled as a special integral transformation, where the spectral sensitivities of the photo receptors represent the base functions of the transformation. It is shown that different sets of photo receptors show the same perception, when their spectral sensitivities are linear dependent. On the other hand, photo receptors with no linear dependency show different perception and there is no analytical transformation between them. Thus, a perfect color correction is only possible if photo sensor and human perception show a linear dependency. In case of dissentient sensor characteristics, the correction method of spectral reconstruction can determine an optimal solution using a least square error optimization. Applying sensors with more than three color channels, this correction method can show improved results due to a better approximation. For implementation of the color correction scheme, different sensor designs have been developed. Compared with currently dominating CCD (Charge Coupled Device) technology, a realisation of image sensors based on CMOS technology show a high potential. CMOS technology allow the integration of the sensor together with control and image processing on the same chip, thus enabling the design of sensor systems at low cost. But modern sub-100nm technologies show also substantial disadvantages, such as increased leakage currents. Special circuit designs have been developed to especially reduce the influence of leakage currents. For application of the color correction method, new multi-channel photo sensors using vertically stacked photo diodes have been developed. The work further shows different concepts of multi-channel sensors capable of high quality color rendition. This approach is demonstrated on several new CMOS sensor designs with examples, implemented in a 90nm Infineon technology.