A sensor node 'AccuMicroMotion' is proposed that has the ability to detect motion in 6 degrees of freedom for the application of physiological activity monitoring. It is expected to be light weight, low power, small and cheap. The sensor node may collect and transmit 3 axes of acceleration and 3 axes of angular rotation signals from MEMS transducers wirelessly to a nearby base station while attached to or implanted in human body. This dissertation proposes a wireless electronic system-on-a-single-chip to implement the sensor in a traditional CMOS process. The system is low power and may operate 50 hours from a single coin cell battery. A CMOS readout circuit, an analog to digital converter and a wireless transmitter is designed to implement the proposed system. In the architecture of the 'AccuMicroMotion' system, the readout circuit uses chopper stabilization technique and can resolve DC to 1 KHz and 200 nV signals from MEMS transducers. The base band signal is digitized using a 10-bit successive approximation register analog to digital converter. Digitized outputs from up to nine transducers can be combined in a parallel to serial converter for transmission by a 900 MHz RF transmitter that operates in amplitude shift keying modulation technique. The transmitter delivers a 2.2 mW power to a 50 Ù antenna. The system consumes an average current of 4.8 mA from a 3V supply when 6 sensors are in operation and provides an overall 60 dB dynamic range. Furthermore, in this dissertation, a methodology is developed that applies accelerated electrical stress on MOS devices to extract BSIM3 models and RF parameters through measurements to perform comprehensive study, analysis and modeling of several analog and RF circuits under hot carrier and breakdown degradation.

Este trabalho apresenta o desenvolvimento de uma nova ferramenta para a síntese automática de células, a partir de uma descrição estrutural no nível lógico. A ferramenta esta sendo integrada ao sistema TRAMO3, e visa eliminar a necessidade do use de biblioteca de células na geração de circuitos. Uma revisão sobre síntese de leiaute e metodologias de projeto é apresentada. A metodologia TRANCA é descrita de forma sucinta e os sistemas TRAMO2 e TRAMO3, assim como o roteador MARTE são analisados em detalhe para indicar o contexto onde se insere o trabalho. As principais alternativas para a geração de células são analisadas e o algoritmo descrito em [REI 93b] é utilizado com algumas modificações, levando em conta situações praticas. Os seguintes passos são executados durante o processo: posicionamento dos transistores, roteamento das conexões internas e compactação do leiaute. Finalmente, alguns melhoramentos no gerador são propostos, de forma a eliminar algumas restrições impostas na primeira versão. / This work presents the development of a new tool for automatic cell synthesis, starting from a structural description at the logic level. The tool is currently being integrated to TRAMO3 system, and aims at eliminating the need of cell libraries utilization during the circuit generation. A brief review about layout synthesis and design methodologies is presented. TRANCA design approach is briefly described and the TRAMO2 and TRAMO3 systems, as well as the MARTE router are analyzed with some detail in order to show the environment where the work is inserted. The main alternatives for cell generation are analyzed and the algorithm described in [REI 93b] is used with some changes, taking into account practical situations. The following steps are executed during the process: transistor placement, routing of internal connections and layout compaction. Finally, some improvements to the generator are proposed, in order to remove some restrictions imposed in the first version.

Este trabalho apresenta o desenvolvimento de uma nova ferramenta para a síntese automática de células, a partir de uma descrição estrutural no nível lógico. A ferramenta esta sendo integrada ao sistema TRAMO3, e visa eliminar a necessidade do use de biblioteca de células na geração de circuitos. Uma revisão sobre síntese de leiaute e metodologias de projeto é apresentada. A metodologia TRANCA é descrita de forma sucinta e os sistemas TRAMO2 e TRAMO3, assim como o roteador MARTE são analisados em detalhe para indicar o contexto onde se insere o trabalho. As principais alternativas para a geração de células são analisadas e o algoritmo descrito em [REI 93b] é utilizado com algumas modificações, levando em conta situações praticas. Os seguintes passos são executados durante o processo: posicionamento dos transistores, roteamento das conexões internas e compactação do leiaute. Finalmente, alguns melhoramentos no gerador são propostos, de forma a eliminar algumas restrições impostas na primeira versão. / This work presents the development of a new tool for automatic cell synthesis, starting from a structural description at the logic level. The tool is currently being integrated to TRAMO3 system, and aims at eliminating the need of cell libraries utilization during the circuit generation. A brief review about layout synthesis and design methodologies is presented. TRANCA design approach is briefly described and the TRAMO2 and TRAMO3 systems, as well as the MARTE router are analyzed with some detail in order to show the environment where the work is inserted. The main alternatives for cell generation are analyzed and the algorithm described in [REI 93b] is used with some changes, taking into account practical situations. The following steps are executed during the process: transistor placement, routing of internal connections and layout compaction. Finally, some improvements to the generator are proposed, in order to remove some restrictions imposed in the first version.

Este trabalho apresenta o desenvolvimento de uma nova ferramenta para a síntese automática de células, a partir de uma descrição estrutural no nível lógico. A ferramenta esta sendo integrada ao sistema TRAMO3, e visa eliminar a necessidade do use de biblioteca de células na geração de circuitos. Uma revisão sobre síntese de leiaute e metodologias de projeto é apresentada. A metodologia TRANCA é descrita de forma sucinta e os sistemas TRAMO2 e TRAMO3, assim como o roteador MARTE são analisados em detalhe para indicar o contexto onde se insere o trabalho. As principais alternativas para a geração de células são analisadas e o algoritmo descrito em [REI 93b] é utilizado com algumas modificações, levando em conta situações praticas. Os seguintes passos são executados durante o processo: posicionamento dos transistores, roteamento das conexões internas e compactação do leiaute. Finalmente, alguns melhoramentos no gerador são propostos, de forma a eliminar algumas restrições impostas na primeira versão. / This work presents the development of a new tool for automatic cell synthesis, starting from a structural description at the logic level. The tool is currently being integrated to TRAMO3 system, and aims at eliminating the need of cell libraries utilization during the circuit generation. A brief review about layout synthesis and design methodologies is presented. TRANCA design approach is briefly described and the TRAMO2 and TRAMO3 systems, as well as the MARTE router are analyzed with some detail in order to show the environment where the work is inserted. The main alternatives for cell generation are analyzed and the algorithm described in [REI 93b] is used with some changes, taking into account practical situations. The following steps are executed during the process: transistor placement, routing of internal connections and layout compaction. Finally, some improvements to the generator are proposed, in order to remove some restrictions imposed in the first version.

L’objectif de ce travail de thèse est le développement en technologie intégrée standard d’une structure de ligne de transmission optimisée en termes de pertes, d’encombrement, de facteur de qualité et surtout du choix du niveau de couplage aux fréquences millimétriques. Cette structure a été nommée CS-CPW (Coupled Slow-wave CoPlanar Waveguide). Dans un premier temps, la théorie ainsi que les modèles électriques des CS-CPW sont présentés. Grâce aux modèles et aux simulations électromagnétiques, des coupleurs directionnels avec plusieurs valeurs de couplage (3 dB, 10 dB, 18 dB) ont été conçus en technologie BiCMOS 55 nm. Ils présentent tous une très bonne directivité, elle est toujours supérieure à 15 dB. Un premier prototype de coupleur a été mesuré à 150 GHz. Dans un deuxième temps, des filtres à la base des lignes couplées ont été développés à 80 GHz en utilisant des lignes CS-CPW. Les résultats des simulations présentent des résultats concurrentiels avec l’état de l’art : 11% de bande passante relative et un facteur non-chargé autour de 25. Finalement, trois projets ont démarré à la base de ces lignes. Ces projets sont actuellement utilisés dans deux travaux de thèse et un stage : un RTPS à 47 GHz, un isolateur à 75 GHz et un balun à 80 GHz. / This work focuses on high-performances CS-CPW (Coupled Slow-wave CoPlanar Waveguide) transmission lines in classical CMOS integrated technologies for the millimiter-wave frequency band. First, the theory as well as the electrical models of the CS-CPW are presented. Thanks to the models and electromagnetic simulations, directional couplers with different coupling levels (3 dB, 10 dB, 18 dB) were designed in BiCMOS 55 nm technology. They have a good directivity, always better than 15 dB. A first prototype of a coupler was measured at 150 GHz presenting good agreement with the simulations. Next, coupled-line base filters were developed at 80 GHz using the CS-CPWs. Simulation present competitive results with the state-of-art: 11% of fractional bandwidth and a unload quality factor of 25. Finally, three projects started based on the CS-CPWs. The projects are currently used in two theses and one internship: a RTPS at 47 GHz, an isolator at 75 GHz and a balun at 80 GHz.

Avec la diminution du nœud de la technologie CMOS, la puissance statique et dynamique augmente spectaculairement. It est devenu l'un des principaux problèmes en raison de l'augmentation du courant de fuite et de la longue distance entre les mémoires et les circuits logiques. Au cours des dernières décennies, les dispositifs de spintronique, tels que la jonction tunnel magnétique (JTM) écrit par transfert de spin, sont largement étudiés pour résoudre le problème de la puissance statique grâce à leur non-volatilité. L'architecture logic-in-memory (LIM) hybride permet de fabriquer les dispositifs de spintronique au-dessus des circuits CMOS, réduisant le temps de transfert et la puissance dynamique. Cette thèse vise à la conception de circuits logiques et mémoires pour le système de faible puissance, en combinant les technologies JTM et CMOS. En utilisant un modèle compact JTM et le design-kit CMOS de STMicroelectronics, nous étudions les circuits hybrides MTJ/CMOS de 1-bit et multi-bit, y compris les opérations de lecture et d'écriture. Les méthodes d'optimisation sont également introduites pour améliorer la fiabilité, ce qui est extrêmement important pour les circuits logiques où les blocs de correction d'erreur ne peuvent pas être facilement intégrés sans sacrifier leurs performances ou augmenter la surface de circuit. Nous étendons la structure MTJ/CMOS hybride de multi-bit à la conception d’une mémoire MRAM avec les circuits périphériques simples. Basés sur le concept de LIM, les circuits logiques/arithmétiques non-volatiles sont conçus. Les JTMs sont intégrés non seulement comme des éléments de stockage, mais aussi comme des opérandes logiques. Tout d'abord, nous concevons et analysons théoriquement les portes logiques non-volatiles (PLNVs) comprenant NOT, AND, OR et XOR. Ensuite, les additionneurs complets non-volatiles (ACNVs) de 1-bit et 8-bit sont proposés et comparés avec l'additionneur classique basé sur la technologie CMOS. Nous étudions l'effet de la taille de transistor CMOS et des paramètres de JMT sur les performances d’ACNV. De plus, nous optimisons l’ACNV sous deux faces. Premièrement, un circuit de détection (mode de tension) de très haute fiabilité est proposé. Après, nous proposons de remplacer le JTM à deux électrodes par un JTM à trois électrodes (écrit par transfert de spin assisté par l’effet Hall de spin) en raison du temps d'écriture et de la puissance plus petit. Basé sur les PLNVs et ACNVs, d'autres circuits logiques peuvent être construits, par exemple, soustracteur non-volatile. Enfin, une mémoire adressable par contenu non-volatile (MACNV) est proposée. Deux décodeurs magnétiques visent à sélectionner des lignes et à enregistrer la position de recherche dans un état non-volatile. / With the shrinking of CMOS (complementary metal oxide semi-conductor) technology, static and dynamic power increase dramatically and indeed has become one of the main challenges due to the increasing leakage current and long transfer distance between memory and logic chips. In the past decades, spintronics devices, such as spin transfer torque based magnetic tunnel junction (STT-MTJ), are widely investigated to overcome the static power issue thanks to their non-volatility. Hybrid logic-in-memory (LIM) architecture allows spintronics devices to be fabricated over the CMOS circuit plane, thereby reducing the transfer latency and the dynamic power dissipation. This thesis focuses on the design of hybrid MTJ/CMOS logic circuits and memories for low-power computing system.By using a compact MTJ model and the STMicroelectronics design kit for regular CMOS design, we investigate the hybrid MTJ/CMOS circuits for single-bit and multi-bit reading and writing. Optimization methods are also introduced to improve the reliability, which is extremely important for logic circuits where error correction blocks cannot be easily embedded without sacrificing their performances or adding extra area to the circuit. We extend the application of multi-context hybrid MTJ/CMOS structure to the memory design. Magnetic random access memory (MRAM) with simple peripheral circuits is designed.Based on the LIM concept, non-volatile logic/arithmetic circuits are designed to integrate MTJs not only as storage elements but also as logic operands. First, we design and theoretically analyze the non-volatile logic gates (NVLGs) including NOT, AND, OR and XOR. Then, 1-bit and 8-bit non-volatile full-adders (NVFAs), the basic elements for arithmetic operations, are proposed and compared with the traditional CMOS-based full-adder. The effect of CMOS transistor sizing and the MTJ parameters on the performances of NVFA is studied. Furthermore, we optimize the NVFA from two levels. From the structure-level, an ultra-high reliability voltage-mode sensing circuit is used to store the operand of NVFA. From the device-level, we propose 3-terminal MTJ switched by spin-Hall-assisted STT to replace the 2-terminal MTJ because of its smaller writing time and power consumption. Based on the NVLGs and NVFAs, other logic circuits can be built, for instance, non-volatile subtractor.Finally, non-volatile content addressable memory (NVCAM) is proposed. Two magnetic decoders aim at selecting a word line to be read or written and saving the corresponding search location in non-volatile state.

Le substrat SOI (Silicon-On-Insulator) constitue aujourd’hui le support de choix pour la fabrication de fonctions optiques compactes. Cette plateforme commune avec la micro-électronique favorise l’intégration de circuits photoniques avec des circuits CMOS. Néanmoins, si le silicium peut être utilisé de manière très avantageuse pour la fabrication de composants optiques passifs, il présente l’inconvénient d’être un très mauvais émetteur de lumière. Ceci constitue un obstacle majeur au développement de sources d’émission laser, briques de constructions indispensables à la fabrication d’un circuit photonique. La solution exploitée dans le cadre de cette thèse consiste à reporter sur SOI des épitaxies laser III-V par collage direct SiO2-SiO2. L’objectif est de réaliser sur SOI des sources lasers à cavité horizontale permettant d’injecter au moins 1mW de puissance dans un guide d’onde silicium inclus dans le SOI. Notre démarche est de transférer un maximum des fonctions du laser vers le silicium, dont les procédés sont familiers au monde de la micro-électronique. Dans l’idéal, le III-V ne devrait être utilisé que comme matériau à gain ; la cavité laser pouvant être fabriquée dans le silicium. Mais cette ligne de conduite n’est pas forcément aisée à mettre en œuvre. En effet, les photons sont produits dans le III-V mais doivent être injectés dans un guide silicium placé sous l’épitaxie. La difficulté est que les deux matériaux sont séparés par plus d’une centaine de nanomètres d’oxyde de collage faisant obstacle au transfert de photons. Le développement de lasers III-V couplés à un guide d’onde SOI demande alors de nouvelles conceptions du système laser dans son ensemble. Notre travail a donc consisté à concevoir un laser hybride III-IV / silicium se pliant aux contraintes technologiques du collage. En s’appuyant sur la théorie des modes couplés et les concepts des cristaux photoniques, nous avons imaginé, réalisé, puis caractérisé un laser à contre-réaction distribuée hybride (en anglais : « distributed feedback laser », laser DFB). Son fonctionnement optique original, permet à la fois un maximum de gain et d’efficacité de couplage grâce à une circulation en boucle des photons du guide III-V au guide SOI. Sur ces dispositifs, nous montrons une émission laser monomode (SMSR de 35 dB) à température ambiante en pompage optique et électrique pulsé. Comme attendu, la longueur d’onde d’émission est dépendante du pas de réseau DFB. Les lasers fonctionnent avec une épaisseur de collage de silice de 200 nm, ce qui offre une grande souplesse quant au procédé d’intégration. Tous les lasers fonctionnent jusqu’à des longueurs de 150 μm (la plus petite longueur prévue sur le masque). Malgré les faibles niveaux de puissances récoltés dans la fibre lors des caractérisations, la prise en compte des pertes optiques induites pas les coupleurs fibres nous indique que la puissance réellement injectée dans le guide silicium dépasse le milliwatt. Notre objectif de ce point de vue est donc rempli. Malheureusement le fonctionnement des lasers en injection électrique continue n’a pas pu être obtenu dans les délais impartis. Cependant, les faibles densités de courant de seuil mesurées en injection pulsée (300A / cm2 à température ambiante sur les lasers de 550 μm de long) laissent présager un fonctionnement prochain en courant continu. / Silicon-On-Insulator (SOI) is today the utmost platform for the fabrication of compact optical functions. This common platform with microelectronics favors the integration of photonic circuits with CMOS circuits. Nevertheless, if silicon allows for the fabrication of compact passive photonic functions, its poor light emission properties constitute a major obstacle to the development of an integrated laser source. The solution used within the framework of this thesis consists in integrating III-IV laser stacks on 200 mm SOI wafers by the mean of SiO2-SiO2 direct bonding. The aim of this work is to demonstrate a III-V on SOI laser that couples at least 1mW to a silicon waveguide. Our approach is to transfer a maximum of the laser complexity to the silicon, which processes are familiar to microelectronics. Ideally, III-V should be just used as a gain material ; the laser cavity being made out of silicon. However, this approach is not so easy to put into practice. Indeed, photons are generated by the III-V waveguide but have to be transferred into the silicon waveguide located under the stack. The difficulty is that both waveguides are separated by a low index bonding layer, which thickness ranges from one hundred to several hundreds of nanometres. The development of a III-V on SOI laser then requires a new thinking of the whole laser system. Therefore, our work has consisted in designing a III-V on silicon hybrid laser that takes into consideration the specific constraints of the integration technology. Based on the coupled mode theory and on the photonic crystals concepts, we have designed, fabricated and characterized an hybrid Distributed Feedback Laser (DFB). Its original work principle allows for both a high amount of gain and coupling efficiency, thanks to a continuous circulation of photons from the III-V to the SOI waveguide. On these devices, we show a monomode laser emission at room temperature (with a side mode suppression ratio of 35dB) under pulsed optical and electrical pumping. As expected, the lasing wavelength is function of the DFB grating pitch. The lasers work with a bonding layer as thick as 200nm, that greatly relaxes the constraints of the bonding technology. Lasers work down to a minimum length of 150 μm, which is the shortest laser lenght of the mask. Despite the low power levels collected by the fibre during the characterizations, accounting for the high optical losses due to the fiber couplers, the optical power effectively injected to the silicon waveguide should be in the miliwatt range. Unfortunately, the low threshold current densities measured under pulsed operation (300 A / cm2 at room temperature) suggest that the continuous-wave regime should be reached in a very near future.

L’intégration monolithique hétérogène de composants III-N sur silicium (Si) offre de nombreuses possibilités en termes d’applications. Cependant, gérer l’hétéroépitaxie de matériaux à paramètres de maille et coefficients de dilatation très différents, tout en évitant les contaminations, et concilier des températures optimales de procédé parfois très éloignées requière inévitablement certains compromis. Dans ce contexte, nous avons cherché à intégrer des transistors à haute mobilité électronique (HEMT) à base de nitrure de Gallium (GaN) sur substrat Si par épitaxie sous jets moléculaires (EJM) en vue de réaliser des circuits monolithiques GaN sur CMOS Si. / The monolithic integration of heterogeneous devices and materials such as III-N compounds with silicon (Si) CMOS technology paves the way for new circuits applications and capabilities for both technologies. However, the heteroepitaxy of such materials on Si can be challenging due to very different lattice parameters and thermal expansion coefficients. In addition, contamination issues and thermal budget constraints on CMOS technology may prevent the use of standard process parameters and require various manufacturing trade-offs. In this context, we have investigated the integration of GaN-based high electron mobility transistors (HEMTs) on Si substrates in view of the monolithic integration of GaN on CMOS circuits.