Spin Torque Oscillator (STO) is a promising technology for microwave and radar applications due to its large tunability, miniature size, high operation frequency, high integration level, etc. However, the technology comes also with issues and challenges,such as low output power and spectrum impurity. For instance, in order to apply the STO technology into communication systems, an amplifier is required to compensate the STO’s low output power.     This thesis presents an amplifier for promising Magnetic Tunnel Junction (MTJ) STO devices. The motional resistance of different MTJ STO devices varies from several Ohms to hundreds Ohms, which makes the design challenging. This thesis focuses first on extracting the amplifier requirements using the state-of-the-art MTJ STO devices. The operation frequency of MTJ STO is in the range of 4-8GHzwith a -40～-60 dBm output power. Therefore, a wideband amplifier with 45-65 dB gain is required. Then based on the amplifier requirements, an amplifier topology is proposed, which is composed of two types of input balun-LNA stages depending onthe motional resistance of the STO, a broadband limiting amplifier and an outputbuffer. CG-CS architecture is suitable for the input balun-LNA in the small motional resistance case and cascoded-CS architecture is suitable for the large motional resistance case. The limiting amplifier and the output buffer are the common circuits shared by two cases via switches.     The wideband amplifier for STO is implemented using a 65nm CMOS process with 1.2 V supply and it exhibits 52.36 dB gain with 1.34-11.8 GHz bandwidth insmall motional resistance case and 59.29 dB gain with 1.171-8.178 GHz bandwidth in large motional resistance case. The simulation results show that the amplifier has very low power consumption and meets the linearity and noise performance requirements.

A novel hierarchical flexing and stretching strategy for rigid semiconducting substrates was devised. Architectures for comprehensively compliant semiconductors were created as a result. Si and GaN-on-Si have been segmented into both highly flexible and rigid segments. An advanced controlled cleavage technique has been integrated into the manufacturing process. The bending radius of the substrate has been decoupled from the substrate thickness thus allowing for higher mechanical stability, while achieving bending radii below 250 .m. Novel fabrication workflows have been created, one of which is completely compatible with CMOS fabrication techniques, while still being cost effective. Each of the rigid segments have been designed to carry in excess of its own weight. The reliability of the interconnecting springs was examined by rugged cyclic bending and twisting tests. Finite element simulations in COMSOL exhibited no stress for the rigid segments. For the first time a flexible and/or stretchable Si substrate has been integrated with pick and place tool technology. Additionally the platform serves as a More-than-Moore technology, by folding the monocrystalline substrate on top of itself, while routing power through the flexible segments. This More-than-Moore (MtM) technology has the advantages of System-in-Package (SiP) but does not have the additional costs. From this compliant approach a qubic 4D electronic platform was created. An aerially deployable electronic system was achieved by incorporating thermal paste into the qubic platform. Energy storage, sensing, and actuating were successfully tested on the system. Buried cavities for microfluidics were developed for on-chip chemical and biological processes. A platform was developed for µTF-SOFCs deposition. Cavities were interconnected subterraneously and columnar anodes were developed to enhance the fuel flow in the fuel cell electrode. The triple phase boundary (TPB) was enhanced by over an order of magnitude in comparison to standard processing techniques. A subsequent, microfluidic platform was developed for biological applications. The wettability of the platform gave good results for water, as well as for neurobasal media buffer. Tests indicate that neurons can grow directly on the platform.

Stochastic iterative decoding is a novel method to decode the bits received at the end of a communication channel and to control the rate of error happening in the message bits due to noise being injected into the channel. This decoder uses stochastic computation that is based on manipulation of probabilities from a random sequence of digital bits. Hardware needed for implementing this arithmetic is very simple and can be completely implemented using simple digital complementary metal oxide gates. This helps the decoder to be technology independent, which is a major advantage over its digital and analog counterparts, which are complex and technology dependent. But this decoder presents a new set of problems when nodes in stochastic decoders can get locked to a fixed state if the stochastic streams are correlated due to the presence of cycles in a decoder's factor graph. To overcome this problem, additional logic has to be introduced on every edge of the decoder to break this correlation. This work presents application-specific-integrated-circuit (ASIC) design and simulation of the digital core of a stochastic iterative decoder in 0.18um technology (Spec- tre). This thesis also examines gate complexity and power onsumption of the decoder with edge-memory, tracking forecast memory, and dual-counter hysteresis techniques in place.

京都大学 / 0048 / 新制・課程博士 / 博士(情報学) / 甲第19137号 / 情博第583号 / 新制||情||102(附属図書館) / 32088 / 京都大学大学院情報学研究科通信情報システム専攻 / (主査)教授 小野寺 秀俊, 教授 髙木 直史, 教授 佐藤 高史 / 学位規則第4条第1項該当 / Doctor of Informatics / Kyoto University / DFAM

Continued technology scaling has introduced many new challenges in VLSI design. Instantaneous switching of the gates yields high current flow through them that causes large voltage drop at the supply lines. Such high instantaneous currents and voltage drop cause reliability and performance degradation. Reliability is an issue as high magnitude of current can cause electromigration, whereas, voltage drop can slow down the circuit performance. Therefore, designing power supply lines emphasizes the need of computing maximum current through them. However, the development of digital integrated circuits in short design cycle requires accurate and fast timing and power simulation. Unfortunately, simulators that employ device modeling methods, such as HSPICE are prohibitively slow for large designs. Therefore, methods which can produce good maximum current estimates in short times are critical. In this work a compact model has been developed for maximum current estimation that speeds up the computation by orders of magnitude over the commercial tools.

A relatively new picosatellite standard, CubeSats have traditionally been used for simple educational missions. As CubeSats become more complex and utilize more complex sensors such as imagers, they gain enhanced credibility as satellite platforms. Imaging systems on CubeSats have the potential to be used for a variety of uses, such as earth and weather monitoring, attitude determination, and remote sensing. However the size and power limitations of CubeSats pose an interesting challenge to the design of a capable, robust imaging system. This thesis outlines the objectives and requirements of CP-3’s imaging system, and describes the development process and methods. Test results from the imaging system are included, as well as lessons learned gleaned from CP-3’s on-orbit operations. This document can serve as a guideline for other teams wishing to develop imaging systems. While other developers may have different requirements or constraints, this roadmap illustrates each of the many considerations that must be taken into account when designing an imaging system.

Fluorescence lifetime imaging (FLIM) has the potential to provide rapid screening and detection of diseases. However, time-resolved fluorescence measurements require high-performance detectors with single-photon sensitivity and sub-nanosecond time resolution. These systems should also be compact, reliable, inexpensive, and easily deployable for laboratory and clinical applications. It is with these applications in mind that the development of single photon avalanche diodes (SPAD) and time-to-digital converter (TDC) prototype integrated circuits (IC) in standard digital CMOS have been pursued in this thesis. SPAD and TDC ICs were designed and fabricated in 130 nm IBM CMOS technology and then intensively studied. Several different SPAD pixels were modeled and designed, and the electro-optical performance was characterized and comparatively studied. By repurposing existing design layers of a standard CMOS process, the fabricated SPAD pixel test structures achieved up to 20× improvement of dark count rate (DCR) compared to previous designs. Optical measurements also showed up to 10× improvement in the detection limits for low-level light. Detailed dark noise characterization was performed at various temperatures using free-running and time-gated modes of operation. Optimal operating conditions were found for minimal afterpulsing effects. The SPAD’s capability to accurately measure fast fluorescence decays was also demonstrated in a practical setting with the lifetime measurements of two fluorophores, Rhodamine 6G and Ruby crystal, which have fluorescence lifetimes of approximately 4 ns and 3 ms, respectively. A fast and accurate TDC prototype circuit for time-correlated single-photon counting (TCSPC) applications was designed, fabricated and characterized. With a coarse-fine delay line architecture, the TDC size was reduced without compromising its linearity and jitter performance. Extensive characterization of the fabricated SPAD and TDC ICs shows that the measured performance met the stated design goals. / Thesis / Doctor of Philosophy (PhD)

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