Binary multiplier has been a staple in the digital circuit design. It is used in microprocessor design, DSP applications etc. Here, we discuss the design of a novel multiplier that employs a modified shift and add logic to multiply two n-bit unsigned binary numbers. In our work, we changed the shift and add algorithm. We used a barrel shifter and a multiplexer to generate the partial products. We also found out a way to reduce the number of partial products so that we would have fewer numbers to add after we generated all of them. An array of Carry Save Adders (CSA) is used to add the partial products. With all our arrangements and setups, we aim to reduce delays and make the design as efficient as possible. As examples, we have shown it to multiply two 16-bit numbers, however, the design can easily be either scaled up or down according to the environment the multiplier is being used.

Superconducting nanowire single-photon detectors are the most promising technology in quantum photon information. They offer high speed, high detection efficiency, low dark count rate as well as low timing jitter compared to other single photon detection solutions. Since the recent advances in photonic quantum computing, the drive for improvement of the implementation complexity, performance and scalability of quantum photon detection has increased. This presents challenges with the current device readout schemes and alternative solutions are required. One of the key parameters to improve the scalability of superconducting nanowire single-photon detectors, is reducing the power dissipation per pixel. This is especially important in cryogenic readouts, where the performance of electronic components changes compared to room temperature. Moreover, the performance of a cryogenic superconducting nanowire single-photon detector readout is dependent both on the device and readout electronics level characteristics, and both must be fine-tuned for desired performance. A solution to the scalability of superconducting nanowire single-photon detectors (SNSPDs) is the development of a readout scheme with minimized power dissipation. We propose a fully digital readout scheme interfaced with a superconducting nanowire single-photon detector (SNSPD), that allows photon detection and reset. For this purpose, a digital single-pixel SiGe Bi-CMOS readout is designed, simulated, and characterised. An improved readout scheme is proposed with an addition of a die resistor to allow a full reset of the detector. / Supraledande nanotrådsdetektorer baserade på enstaka fotoner är ett av de mest avancerade koncepten inom kvantfotoninformationsteknik. Syftet med att utveckla denna teknik är att förbättra egenskaper så som komplexiteten, prestandan och skalbarheten. En av de viktigaste parametrarna för att förbättra skalbarheten hos supraledande nanotrådsdetektorer med enstaka fotoner är att minska energiförbrukningen per pixel. Detta är särskilt viktigt i kryogena avläsningar, där prestandan hos elektroniska komponenter förändras jämfört med rumstemperatur. Dessutom, beror prestandan hos en kryogen supraledande nanotrådsdetektor både på komponenten och på avläsningselektroniken,och båda måste finjusteras för att uppnå önskad prestanda. En lösning på kalbarheten för supraledande nanotrådsdetektorer med enstaka fotoner (SNSPDs) är att realisera avläsning med minimerad effektförlust. Vi föreslår en helt digital avläsning som är kopplad till en supraledande enfoton nanotrådsdetektor (SNSPD), som gör det möjligt att detektera fotoner och att återställa detektorn efter avläsning. För detta ändamål, designades, simuleras och karakteriserades en digital avläsningkrets med en enda pixel. Ett förbättrat avläsningssystem föreslås genom att lägga till ett diskret motstånd för att möjliggöra en fullständig återställning av detektorn.

Many modern digital systems use forms of CMOS logical implementation due to the straight forward design nature of CMOS logic and minimal device area since CMOS uses fewer transistors than other logic families. To achieve high-performance requirements in mixed-signal chip development and quiet, noiseless circuitry, this thesis provides an alternative toCMOSin the form of MOS Current Mode Logic (MCML). MCML dissipates constant current and does not produce noise during value changing in a circuit CMOS circuits do. CMOS logical networks switch during clock ticks and with every device switching, noise is created on the supply and ground to deal with the transitions. Creating a noiseless standard cell library with MCML allows use of circuitry that uses low voltage switching with 1.5V between logic levels in a quiet or mixed-signal environment as opposed to the full rail to rail swinging of CMOS logic. This allows cohesive implementation with analog circuitry on the same chip due to constant current and lower switching ranges not creating rail noise during digital switching. Standard cells allow for the Cadence tools to automatically generate circuits and Cadence serves as the development platform for the MCML standard cells. The theory surrounding MCML is examined along with current and future applications well-suited for MCML are researched and explored with the goal of highlighting valid candidate circuits for MCML. Inverters and NAND gates with varying current drives are developed to meet these specialized goals and are simulated to prove viability for quiet, mixed-signal applications. Analysis and results show that MCML is a superior implementation choice compared toCMOSfor high speed and mixed signal applications due to frequency independent power dissipation and lack of generated noise during operation. Noise results show rail current deviations of 50nA to 300nA during switching over an average operating current of 20µA to 80µA respectively. The multiple order of magnitude difference between noise and signal allow the MCML cells to dissipate constant power and thus perform with no noise added to a system. Additional simulated results of a 31-stage ring oscillator result in a frequency for MCML of 1.57GHz simulated versus the 150.35MHz that MOSIS tested on a fabricated 31-stage CMOS oscillator. The layouts designed for the standard cell library conform to existing On Semiconductor ami06 technology dimensions and allow for design of any logical function to be fabricated. The I/O signals of each cell operate at the same input and output voltage swings which allow seamless integration with each other for implementation in any logical configuration.