In this thesis, we introduce the fundamental operation of intra-body communications. The efficiency of the intra-body communications and the disturbance of intra-body communication are also studied. Intra-body communications propagate the signal by using the surface of human skin. Our study is mainly based on simulation. The accuracy of the simulation is verified by comparing with results in two papers. Then, five tissues are used to represent in the simulation. Firstly, we find design rules of transmitter and receiver for improving efficiency. The larger size of the circuit board is, the stronger signal receives. Length is more sensitivity than width but electrodes cannot be close. The signal does not vary widely with the location of the receiver. By setting proper parameters of skin, we can differentiate between wet skin and dry skin. Because the conductivity of wet skin is higher than dry one, the wet skin will give a stronger received signal. In the latter part of the thesis, we study the parameters cause the disturbance of intra-body communications. First, we study the effects of the person is close to the system. Second, we discuss the changes of the impedance of the system when another person touches the user. In the last, we discuss the variety of the receiving signal due to the bending of the arm, furthermore, we can distinguish the angles of the arm¡¦s bend from the coupling of electric field.

Electronically monitoring whether or not your car block heater is connected to a mains outlet might at first seem like an arbitrary task. A device installed in the comfort of the car seating area, which tells the user at every startup whether or not his/her car is connected to a mains outlet, could have market appeal though. But in order for it to be a worthwhile idea to pursuit, a certain requirement has to be met. It has to be able to be able to accurately detect whether or not the car is connected, through a single connection; the car ground. A certain part of the voltage in the phase of the mains will be capacitively coupled upon the safety ground. By exploiting the fact that the car ground will be connected to the mains safety ground when the block heater cable is in use, a device which can detect that coupled voltage could possibly be developed. In other words, a cable monitoring unit which in actuality detects a connection to the mains safety ground through capacitive coupling, hence the title of this dissertation. This work sets out to taking appropriate measurements to find out whether or not this proposed method of safety ground detection is valid, with heavy emphasis on whether or not it is applicable to a cable monitoring unit. According to the measurement results, an appropriate device is developed. A device which can fill the function described in the previous paragraph. Development of such a device involves; proper method of supplying power which upholds a galvanically isolated floating ground, signal processing, reliable detection mechanism, and considerations to how unintentional capacitive coupling behaves. A theoretical model of the device is put forth, as well as an actual rough prototype to in practice try to prove that the concept and method is valid. Downsides and problems with the device are discussed, such as upholding an effective detection system without making the device hard and cumbersome to use. Possible solutions to these problems are also proposed. The possible future of the concept of this device is also touched upon.

The thesis is composed of two topics: A SOC design for one-time implantable spinal cord stimulation system ¡]SCS¡^, and the design of an inter-chip capacitance coupling circuit. In the first topic, the SOC design using wireless power and data transmission techniques for the SCS system is presented in this work. The proposed SOC can control 4 electrodes to generate different patterns of stimulation waves. It has multiple modes to drive whole the SCS system. Notably, the SOC contains a novel ASK demodulator which converts the ASK signals into digital signals reliably. The SOC is implemented using a typical 0.18-£gm 1P6M CMOS process. The chip area is only 1.71 * 1.41 mm2. Besides, the volume of the implantable SCS pulse generator utilizing this SOC is less than 24 cm3, and the power consumption is only 59.4 mW. In the second topic, a high-speed inter-chip capacitance coupling circuit is presented. Digital signals between two chips can be transceived through capacitive coupling of the proposed circuit. Notably, the transceivers are designed below the capacitors to attain the area reduction. It is an advanced application for high-speed wafer testing and 3D IC communication. A prototype chip is presented to achieve 2 Gbps on silicon using a typical 0.18 £gm 1P6M CMOS process. The chip area is 1045 ¡Ñ 894 £gm2. Besides, it only costs 21.47 mW in terms of power consumption. This capacitive coupling technique for high-speed digital circuit has great potential in the coming future.

More and more electronic products, like battery chargers and power supplies, as well as applications in telecommunications and automotive electronics are based on System-on-Chip solutions, where signal processing and power devices are integrated on the same chip. The integration of different functional units offers many advantages in terms of reliability, reduced power consumption, weight and space reduction, leading to products with better performance at a hopefully lower price. This thesis focuses on the integration of vertical high-voltage double-diffused MOS transistors (DMOSFETs) on Silicon-on-Insulator (SOI) substrates. MOSFETs possess a number of features which makes them indispensable for Power Integrated Circuits (PICs): high switching speed, high efficiency, and simple drive circuits. SOI substrates combined with trench technology is superior to traditional Junction Isolation (JI) techniques in terms of cross-talk and leakage currents. Vertical DMOS transistors on SOI have been manufactured and characterized, and an analytical model for their on-resistance is presented. A description of self-heating and operation at elevated temperatures is included. Furthermore, the switching dynamics of these components is investigated by means of device simulations with the result that the dissipated power during unclamped inductive switching tests is reduced substantially compared to bulk vertical DMOSFETs. A large number of defects is created in the device layer if the trenches are exposed to high temperatures during processing. A new fabrication process with back-end trench formation is introduced in order to minimize defect generation. In addition, a model for the capacitive coupling between trench-isolated structures is developed.

Nesta dissertação é apresentado o estudo dos transistores de porta flutuante (Floating Gate Transistor - FG Transistor), sua modelagem, e a análise do efeito da dose de ionização total (Total Ionizing Dose- TID) sobre os transistores FG. Para isto foi procurado e implementado um modelo de simulação elétrica do transistor FG em condições de leitura (análise DC), baseado no cálculo quantitativo da tensão na porta flutuante em função das tensões nos terminais do transistor, no valor de carga armazenado na porta flutuante e nos coeficientes de acoplamento capacitivo que apresentam este tipo de dispositivos. Para a análise do efeito TID, a tensão limiar do transistor MOS foi variada usando o método de simulação Monte Carlo, tendo em conta as variações da tensão limiar que apresentam os transistores FG submetidos na radiação ionizante. O estudo obteve como resultado a confirmação da perda de carga do FG à medida que é incrementada a dose de radiação, o que implica uma alteração na característica de retenção de carga que caracteriza as células de memórias não voláteis (Non Volatile Memory - NVM). / In this dissertation work, a study of the the floating gate Transistor (FG transistor) performed. The focus in the electrical modeling, and the analysis of the impact of the Total Ionizing Dose (TID) on the electrical performance of the device. Aiming electrical level simulation, different electric simulation models for the FG transistor in read conditions (DC analysis) were evaluated and the model best suited for implementation into the simulation tool was selected. The selected model is based on Floating Gate voltage calculation as a function of polarization voltage of the FG transistor terminals, the stored charge value in the Floating Gate and the capacitive coupling coefficient presented by this device. For the TID analysis the threshold voltage of the MOS transistor was shifted by means of a Monte Carlo simulation method, considering the threshold voltage variations when the FG transistor is subjected to the ionizing radiation.The analysis lead to the confirmation that the loss charge stored in the FG increases with the radiation dose, affecting the retention characteristics of the memory cells.

Nesta dissertação é apresentado o estudo dos transistores de porta flutuante (Floating Gate Transistor - FG Transistor), sua modelagem, e a análise do efeito da dose de ionização total (Total Ionizing Dose- TID) sobre os transistores FG. Para isto foi procurado e implementado um modelo de simulação elétrica do transistor FG em condições de leitura (análise DC), baseado no cálculo quantitativo da tensão na porta flutuante em função das tensões nos terminais do transistor, no valor de carga armazenado na porta flutuante e nos coeficientes de acoplamento capacitivo que apresentam este tipo de dispositivos. Para a análise do efeito TID, a tensão limiar do transistor MOS foi variada usando o método de simulação Monte Carlo, tendo em conta as variações da tensão limiar que apresentam os transistores FG submetidos na radiação ionizante. O estudo obteve como resultado a confirmação da perda de carga do FG à medida que é incrementada a dose de radiação, o que implica uma alteração na característica de retenção de carga que caracteriza as células de memórias não voláteis (Non Volatile Memory - NVM). / In this dissertation work, a study of the the floating gate Transistor (FG transistor) performed. The focus in the electrical modeling, and the analysis of the impact of the Total Ionizing Dose (TID) on the electrical performance of the device. Aiming electrical level simulation, different electric simulation models for the FG transistor in read conditions (DC analysis) were evaluated and the model best suited for implementation into the simulation tool was selected. The selected model is based on Floating Gate voltage calculation as a function of polarization voltage of the FG transistor terminals, the stored charge value in the Floating Gate and the capacitive coupling coefficient presented by this device. For the TID analysis the threshold voltage of the MOS transistor was shifted by means of a Monte Carlo simulation method, considering the threshold voltage variations when the FG transistor is subjected to the ionizing radiation.The analysis lead to the confirmation that the loss charge stored in the FG increases with the radiation dose, affecting the retention characteristics of the memory cells.

Nesta dissertação é apresentado o estudo dos transistores de porta flutuante (Floating Gate Transistor - FG Transistor), sua modelagem, e a análise do efeito da dose de ionização total (Total Ionizing Dose- TID) sobre os transistores FG. Para isto foi procurado e implementado um modelo de simulação elétrica do transistor FG em condições de leitura (análise DC), baseado no cálculo quantitativo da tensão na porta flutuante em função das tensões nos terminais do transistor, no valor de carga armazenado na porta flutuante e nos coeficientes de acoplamento capacitivo que apresentam este tipo de dispositivos. Para a análise do efeito TID, a tensão limiar do transistor MOS foi variada usando o método de simulação Monte Carlo, tendo em conta as variações da tensão limiar que apresentam os transistores FG submetidos na radiação ionizante. O estudo obteve como resultado a confirmação da perda de carga do FG à medida que é incrementada a dose de radiação, o que implica uma alteração na característica de retenção de carga que caracteriza as células de memórias não voláteis (Non Volatile Memory - NVM). / In this dissertation work, a study of the the floating gate Transistor (FG transistor) performed. The focus in the electrical modeling, and the analysis of the impact of the Total Ionizing Dose (TID) on the electrical performance of the device. Aiming electrical level simulation, different electric simulation models for the FG transistor in read conditions (DC analysis) were evaluated and the model best suited for implementation into the simulation tool was selected. The selected model is based on Floating Gate voltage calculation as a function of polarization voltage of the FG transistor terminals, the stored charge value in the Floating Gate and the capacitive coupling coefficient presented by this device. For the TID analysis the threshold voltage of the MOS transistor was shifted by means of a Monte Carlo simulation method, considering the threshold voltage variations when the FG transistor is subjected to the ionizing radiation.The analysis lead to the confirmation that the loss charge stored in the FG increases with the radiation dose, affecting the retention characteristics of the memory cells.

No description available.

Submitted by Lucienne Costa (lucienneferreira@ufcg.edu.br) on 2018-04-17T13:51:49Z No. of bitstreams: 1 HENRIQUE NUNES DE SANTANA – DISSERTAÇÃO (PPGEE) 2017.pdf: 2930914 bytes, checksum: a4c0e297d62f2854c085762512fb6f16 (MD5) / Made available in DSpace on 2018-04-17T13:51:49Z (GMT). No. of bitstreams: 1 HENRIQUE NUNES DE SANTANA – DISSERTAÇÃO (PPGEE) 2017.pdf: 2930914 bytes, checksum: a4c0e297d62f2854c085762512fb6f16 (MD5) Previous issue date: 2017-08-18 / Capes / Neste trabalho, é avaliada aplicabilidade de sensores de acoplamento capacitivo na detecção dos sinais emitidos por arcos elétricos em contatos de disjuntores. Adicionalmente, é investigada a possibilidade de correlacionar estes sinais com nível de degradação dos contatos de arco. A aplicabilidade dos sensores é avaliada por meio da comparação dos sinais detectados pelos mesmos, com os sinais detectados por uma antena direcional em banda larga, tanto no domínio do tempo quanto no domínio da frequência. Para a análise da correlação entre o nível de degradação dos contatos de arco e os sinais detectados, atributos de estatística descritiva da duração e da energia dos sinais foram avaliados. A análise dos resultados evidenciou que os sensores de acoplamento capacitivo são capazes de detectar os sinais emitidos pelos arcos elétricos. Também foi evidenciado que a sensibilidade de detecção dos sensores depende da posição na qual foram instalados ao longo do polo analisado. No caso dos disjuntores utilizados neste trabalho, a melhor posição para a instalação dos sensores foi a posição mais próxima do terminal inferior do polo. A flexibilidade e o valor da constante dielétrica devem ser avaliados no momento da escolha do material empregado na confecção dos sensores, uma vez que sensores pouco flexíveis podem sofrer danos ao serem instalados no polo do disjuntor e, constantes dielétricas elevadas podem prejudicar os ganhos dos respectivos sensores. A correlação entre os sinais dos arcos elétricos detectados pelos sensores e o nível de degradação dos contatos de arco é possível, quando os atributos estatísticos da média, desvio padrão, curtose e mediana obtidos da energia dos referidos sinais são avaliados. / In this work, is evaluated the applicability of capacitive coupling sensors in the detection of signals emitted by electric arcs in circuit breaker contacts. In addition, the possibility of correlating these signals with the arcing contacts degradation level is investigated. The sensors applicability is investigated by comparing the signals detected by them with the signals detected by a broadband directional antenna in both time and frequency domain. For the analysis of the correlation between the arcing contacts degradation level and the detected signals, descriptive statistical attributes of the duration and energy of the signals were evaluated. The analysis of the results showed that the capacitive coupling sensors are able to detect the signals emitted by the electric arcs. It was also evidenced that the sensor detection sensitivity depends on the position in which they are installed along the analyzed pole. In the case of the circuit breakers used in this work, the best position for the installation of the sensors was the one closest to the lower terminal of the pole. The flexibility and value of the dielectric constant must be evaluated when choosing the material used in the construction of the sensors, since weak sensors can be damaged when installed at the pole of the circuit breaker, and high dielectric constants can affect the gains of the respective sensors. The correlation between the electric arcs signals detected by the sensors and the arcing contacts degradation level is possible, when the statistical attributes of the mean, standard deviation, kurtosis and median obtained from the energy of these signals are evaluated.

Switching of shunt reactors and capacitor banks is known to cause a very high rate of rise of transient recovery voltage across the circuit breaker contacts. With improvements in circuit breaker technology, modern SF6 puffer circuits have been designed with less interrupter per pole than previous generations of SF6 circuit breakers. This has caused modern circuit breakers to operate with higher voltage stress in the dielectric recovery region after current interruption. Catastrophic failures of modern SF6 circuit breakers have been reported during shunt reactor and capacitor bank de-energisation. In those cases, evidence of cumulative re-strikes has been found to be the main cause of interrupter failure. Monitoring of voltage waveforms during switching would provide information about the magnitude and frequency of small re-ignitions and re-strikes. However, measuring waveforms at a moderately high frequency require plant outages to connect equipment. In recent years, there have been increasing interests in using RF measurements in condition monitoring of switchgear. The RF measurement technique used for measuring circuit breaker inter-pole switching time during capacitor bank closing is of particular interest. In this thesis, research has been carried out to investigate switching transients produced during circuit breaker switching capacitor banks and shunt reactors using a non-intrusive measurement technique. The proposed technique measures the high frequency and low frequency voltage waveforms during switching operations without the need of an outage. The principles of this measurement technique are discussed and field measurements were carried out at shunt rector and capacitor bank installation in two 275 kV air insulated substations. Results of the measurements are presented and discussed in this thesis. The proposed technique shows that it is relatively easy to monitor circuit breaker switching transients and useful information on switching instances can be extracted from the measured waveforms. Further research works are discussed to realise the full potential of the measuring technique.