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Lab-on-a-chip technology is a rapidly growing research area. Joining together several disciplines, such as physics, biology and several instances of nanotechnologies. The aim of this research is mainly to produce chips that can do the same types of measurements as large lab equipment and measurement systems, but at a fraction of the size and cost. In this work a multifunctional measuring device have been developed. It can measure optical absorbance and fluorescence while performing a range of potentiometric techniques; including chronoamperometry, linear- and cyclic voltammetry. From all these measurements it is possible to calculate particle concentrations in fluid samples. The aim is to bring simpler and cheaper point of care devices to the public. Without larger losses in accuracy and reliability of the medicinal test. To do this our device is intended to be used with lab-chip, which are capable of amplifying the signals while reducing the sample size. Lab-chips could be used in several areas but the ones being designed with this device are made for biomedical purposes, applying suitable nanostructures and reagents to measure the presence of biomarkers. With these techniques, medicinal diagnostics can be made a few minutes after samples have been collected from patients. Much quicker and more direct than sending the samples to a lab and waiting hours if not days for the results. The measuring device or lab-chip reader will use two different lab-chips in the future. One that is optimised for optical absorbance and the other for fluorescence. Both will work with electrochemical measurements, but at present only the absorbance chip have been available for testing and that without any signal enhancing techniques. Assessment of the reader's capabilities was made with solutions of gold nanoparticles, TMB (tetramethylbenzidine), iron dissolved in PBS (Phosphate-buffed saline) and with a film made of PPV (Poly para-phenylenevinylene). The first two were used to test absorbance; while the iron and PBS have been used to test electrochemical system; and the PPV was coated on a glass substrate and used to test fluorescence. During the optical absorption test, it was found that the reader can distinguish between different concentrations of the various solutions. The results are promising and further removal of signal drifts will improve signals considerably. Fluorescence can be induced and measured with the device. This part of the system is, however, untested in general and future work will show if it is sufficient. The iron solution was tested with three different methods. chronopotentiometry, linear sweep voltammetry and cyclic voltammetry. It was however found that our measurements were distorted in comparison with the expected voltammogram for iron in PBS. Additional peaks were found in the voltammogram and it is believed that these are a result of oxidation of the electrodes on the lab-chip.

Asynchronous circuits are usually applied for the communications between multiple clock-domain blocks in some SoCs. According to application-specific traffic, efficiently allocating reasonable buffers in an asynchronous NoC router can avoid the waste or shortage of buffer resource. The method of application-specific asynchronous First-In-First-Out buffer allocation can reduce the silicon area and the power consumption to improve the network latency. According to given traffic pattems, the save of area buffer of our buffer-allocation method can be up to near 30% and the latency is reduced a little at same time. / Bypass schemes is efficient to reduce the average propagation cycles in NoCs. We propose novel lookahead bypass scheme to improve the network latency. The lookahead bypass router is implemented and evaluations of valious configurations are compared, where the proposed architecture significantly improves the packet latency up to 32.1 % over a baseline router. These prove that the router can reduce the average network latency and power consumption, and decreases the reliance on large buffers and virtual channels. Furthermore, the application-specific short-circuit channel is introduced to add some short cuts in a router to bypass the crossbar switch. It can provide additional internal channels to bypass the crossbar and increase the total probability of lookahead bypass. Therefore, the latency can be further reduced. And the throughput can be increased in some applications. / Multicast is preferred in parallel computers. It is an inherent fault of network-on-chip as compared with competitor bus architecture. Software method is a conventional method to implement multicast, but there is a large overhead in latency. The latency overhead of a 4-flit multicast packet achieves 6∼7 times as compared with tree-based or path-based hardware multicast. Hardware multicast support is necessary in these applications. A group-based hardware multicast method is desclibed and estimated in this thesis. Quality of service is also introduced to speed up multicast packets. / On-chip communication infrastructures are inunensely important today. As silicon technology allows more than one billion of transistors in a single piece of silicon, the system-on-chip (SoC) circuits can contain already a large number of processing elements (PEs). Therefore, the Networks-on-Chip (NoCs) are a generally accepted concept to solve the problems such as the scalability and throughput limitation, and physical design problems inherent in dedicated links and shared buses. However, the state-of-the-art on-chip network suffers from latency overhead due to the additional network as compared with dedicated wire connection. According to the different application enviromnents, there are different low-latency technologies for networks-on-chip. This thesis proposes some methods for low-latency NoCs design to relax the latency overhead, which include application-specific asynchronous buffer allocation, hardware multicast support, lookahead bypass scheme and short-circuit crossbar channel optimization. / Xin, Ling. / Adviser: Chui-Sing Choy. / Source: Dissertation Abstracts International, Volume: 73-03, Section: B, page: . / Thesis (Ph.D.)--Chinese University of Hong Kong, 2010. / Includes bibliographical references (leaves 157-164). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [201-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese.

Health-care delivery in developing countries has many challenges because they do not have enough resources for meeting the healthcare needs and they lack testing lab infras- tructures in communities. It has been proven that Point-Of-Care (POC) testing can be considered as one of the ways to resolve the crisis in healthcare delivery in these com- munities. The POC testing is a mission critical processes in which the patient conduct tests outside of laboratory environment and it needs a secure communication system of architecture support which the research refers as POCT system Almost every ten years there will be a new radio access technology (RAT) is released in the wireless communication system evolution which is primarily driven by the 3GPP standards organisation. It is challenging to develop a predictable communication sys- tem in an environment of frequent changes originated by the 3GPP and the wireless operators. The scalable and expandable network architecture is needed for cost-effective network management, deployment and operation of the POC devices. Security mecha- nisms are necessary to address the specific threats associated with POCT system. Se- curity mechanisms are necessary to address the specific threats associated with POCT system. The POCT system communication must provide secure storage and secure com- munication to maintain patient data privacy and security. The Federal Drug Admin- istration (FDA) reports the leading causes of defects and system failures in medical devices are caused by gaps between the requirements, implementation and testing. The research was conducted, and technical research contributions are made to resolve the issues and challenges related to the POCT system. A communication protocol implemented at the application level, independent of radio access technologies. A new methodology was created by combining Easy Approach to Requirement Specifications (EARS) methodology and Use Case Maps (UCM) model which is a new approach and it addresses the concerns raised by the FDA. Secure cloud architecture was created which is a new way of data storage and security algorithms models were designed to address the security threats in the POCT system. The security algorithms, secure cloud architecture and the communication protocol coexist together to provide Radio access technology Independent Secure and Expandable (RISE) POCT system. These are the contributions to new knowledge that came out of the research. The research was conducted with a team of experts who are the subject matter experts in the areas such as microfluidics, bio-medical, mechanical engineering and medicine.

Integrating many processing elements (PE) in a single chip is inevitable as silicon technology allows more than one billion of transistors in a single piece of silicon. Networks-on-Chip (NoCs) has been proposed as a scalable solution to both increasing bandwidth requirements and physical design problems for multi-PE chips. However, as multi-PE chips drive the design focus to shift from the computation-centric to communication-centric, area and power costs consumed by communication has become comparable to what computation consumes. / The second direction is to reduce hop counts of packets when they travel from sources to destinations, and thus to reduce power consumption of NoCs. The reduction of hop counts is realized by using a recently proposed express virtual channel (EVC) technique to virtually bypass intermediate routers. We study the EVC technique in two domains. The first domain is to present a high-level, application-specific methodology to improve power efficiency of EVC paths early in the design stage. The methodology includes three steps. Firstly, aggregate communication loads between routers are calculated. Secondly, an energy reduction model and an energy overhead model are developed. Finally, energy savings of all possible EVCs path are calculated and a greedy algorithm is applied to insert EVCs paths in an iterative way. / The second domain is to exploit the EVC flow control in design and implementation of low-power NoCs. We firstly present cost-efficient hardware components for both EVC source and EVC bypass routers, then propose a statistical approach to customize buffer architectures for EVC networks, then describe creative use of low-power circuit techniques such as clock gating and operand isolation for EVC routers, and finally evaluate EVC NoCs through detailed ASIC implementations. Results show that EVC NoCs can save up to 34.26% of power compared to baseline NoCs. / This thesis tackles design and implementation of cost-efficient NoCs along two orthogonal directions. The first direction is to reduce area and power costs of a single virtual channel router. Through ASIC implementations, we find that allocator logic, including both virtual channel allocator (VA) and switch allocator (SA), consumes a large amount of costs. Based on RTL simulations for the entire NoCs, we identify great opportunities to reduce design costs of VA and then propose two low-complexity allocators: look-ahead VA and combined switch-VC allocator (SVA). Evaluations are performed for a wide range of traffic patterns and router parameters. Results show that both proposed architectures significantly reduce area and power costs of allocators without penalties on network performances. / Zhang, Min. / Source: Dissertation Abstracts International, Volume: 72-01, Section: B, page: . / Thesis (Ph.D.)--Chinese University of Hong Kong, 2010. / Includes bibliographical references (leaves 139-145). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. Ann Arbor, MI : ProQuest Information and Learning Company, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese.

Thesis (Ph. D.)--Washington State University, December 2007. / Includes bibliographical references (p. 107-112).

Thesis (Ph. D.)--Lehigh University, 2006. / Includes vita. Includes bibliographical references (leaves 173-191).

The demands of future computing, as well as the challenges of nanometer-era VLSI design, will require new design techniques and design styles that are simultaneously high performance, energy-efficient, and robust to noise and process variation. One of the emerging problems concerns the communication mechanisms between the increasing number of blocks, or cores, that can be integrated onto a single chip. The bus-based systems and point-to-point interconnection strategies in use today cannot be easily scaled to accommodate the large numbers of cores projected in the near future. Network-on-chip (NoC) interconnect infrastructures are one of the key technologies that will enable the emergence of many-core processors and systems-on-chip with increased computing power and energy efficiency. This dissertation is focused on testing, yield improvement and fault-tolerance of such NoC infrastructures. A fast, efficient test method is developed for NoCs, that exploits their inherent parallelism to reduce the test time by transporting test data on multiple paths and testing multiple NoC components concurrently. The improvement of test time varies, depending on the NoC architecture and test transport protocol, from 2X to 34X, compared to current NoC test methods. This test mechanism is used subsequently to perform detection of NoC link permanent faults, which are then repaired by an on-chip mechanism that replaces the faulty signal lines with fault-free ones, thereby increasing the yield, while maintaining the same wire delay characteristics. The solution described in this dissertation improves significantly the achievable yield of NoC inter-switch channels – from 4% improvement for an 8-bit wide channel, to a 71% improvement for a 128-bit wide channel. The direct benefit is an improved fault-tolerance and increased yield and long-term reliability of NoC based multicore systems.

A Study on the Analysis of Competitive Strategy of Flip Chip Packaging Industry in Taiwan¡X Case Study on S Company Abstract The success of semiconductor industry in Taiwan significantly lies on the complete demarcation of the industry chain by companies involved in each area of IC design, foundry, packaging and testing. Nonetheless, packaging and testing are generally categorized to one industry as the major company usually runs packaging business in line with testing by emphasizing their turn-key solution. However, this concept will not be applied in the future even followed by the quantum breakthrough on the structure of the industry chain. This is a qualitative descriptive study mainly on analysis of competitive advantage and strategy of Flip Chip Packaging Industry in Taiwan. The theme studied is hardly assessed by quantified data. However through the researcher¡¦s macro review of the industry environment as well as micro review of specific individual case with primary and secondary data all-around collected, the present situation, character and trend of the industry are understood by analyzing external environment and internal corporate, searching source of competitive advantage in line with a case study of competitive strategy. The conclusion on future competitive strategy of Flip Chip Packaging Industry in Taiwan based on the case study is followed: 1. Under the trend of global demarcation with analysis, the future operation mode of Taiwan Flip Chip Packaging Industry should be transformed from low skill level to high technique intensive level through virtual integration of packaging and testing from the back end and IC design of the front end, which results in promoting the integration value of industry chain as well as providing the most efficient producing system to the globe. 2. Reviewing the current trend, development and competitors¡¦ competitive strategy of Taiwan Flip Chip Packaging Industry, analysis shows that under the evolution of technique and product, Taiwan Flip Chip Packaging Industry should take advantage of the special needs from IC design industry and IDM factories to devote to technique integration, application and development in the future. In addition the ability to innovate and establish standard will be uplifted with raising competitive from a complete industry chain and advanced foundry advantage. 3. Researching the core competitive from the case study and presenting the future competitive strategy of Taiwan Flip Chip Packaging Industry shows that differentiation directs the competition in line with stepping into production service and production research and development to replace cost advantage. Key Word: Competitive Advantage, Competitive Strategy, Core Source , Flip Chip Package

Modern development of electronic devices requires the integration of more and more powerful functions within the same amount of space. However, this is accompanied by increased difficulties within the manufacturing and packaging processes. A proposal for the arrangement of wire connecting is suggested. In this work, which is to replace the multi-tier design with conventional high & long wire bonding. The advance of bonding layout of the stack die HSBGA (Heat Slug Ball Grid Array) chip assembly can enhance wire bonding with electrical performance by shortening wire length. This promises a better thermal performance of thermal consumption between the function die and heat slugs. This analysis includes simulations of electrical and thermal performance, as well as simulations of drawing layout for an actual production, the bonding looping parameters optimization, and SEM analysis to confirm the results. Based on the above analyses, the results reveal three advantages of the proposal of ¡§Advance bonding layout of chip assembly¡¨ which are: (1)reduction of 40% thermal resistance, (2)£cJC voltage insertion loss improvement of 30~40%, and (3)reduction of the gold wire length from 4.5mm to 3mm, saving 1/3 of gold wire consumption. Overall, assembly costs can be reduced by 6%.