The study of alignment shift in flip chip bonding for VCSEL array was studied experimentally. We calculated the relation between the restoring force and the solder volume by the simulation software PadCAD. The metal pad size were 10£gm, 20£gm, 30£gm in diameter shape and 40£gm in square shape. The solder bump was electroplat by bidirection pulse in the silicon bench which was evaporated by Au/Pt/Ti. The oxidization in the surface of the solder was removed by using flux. The VCSEL array and the Si-bench in flip chip bonding was operated at the temperature 210¢J and 5 seconds. After the flip chip bonding, the minimum alignment shift in X direction was measured to be 2.2£gm. Base on the alignment shift measured result, the maximum coupling efficiency was calculated to be 48% for VCSEL array module.

Abstract The thesis is aimed to simulate the flip chip in chip scale package (FCCSP) by finite element method incorporated with software ANSYS due to thermally cyclic loading. The difference between two-dimensional and tree-dimensional structures is conferred. The position and height of solder bump in FCCSP and cyclic temperature are considered as parameters. The effects of above-mentioned parameters on package¡¦s fatigue models and fatigue damage are studied. The results show that the two-dimensional structure can help us to understand the position of the maximum displacement and the maximum equivalent strain. However, the values of numerical result in the two- dimensional structure are not very accurate. The fatigue fracture will first take place at the top of the most outside solder bump far away from the center of the whole package. If the height of solder bump is lower, the fatigue fracture of solder bump is faster. If the duration time of high and low temperatures is longer, the fatigue fracture due to creep of solder bump becomes faster. When the height of solder bump is change, the change of fatigue damage with plastic strain of solder bump will more obvious than the change of fatigue damage due to creep of solder bump. The extension of duration time of high and low temperatures will increase fatigue damage due to creep of solder bump, but not change the fatigue damage with plastic strain of solder bump. When the height of solder bump is reduced or the duration time of high and low temperatures is extended will increase fatigue damage subjected to cyclic temperature.

Abstract In this study, we use microfabrication processes on silicon to produce a rectangular microchannel. The fabrication technology includes exposing, dry etching, and anodic bounding technologies. After fabrication finished, we use AFM and alpha-step to secure surface roughness. It is found a relatively low surface roughness about 3.34¢H with dimension of 0.5£gm¡Ñ100£gm¡Ñ5000£gm microchannel. A theoretical study and calculations, we also made with continuity equation and proper slip condition to analyze fluid behavior in microchannel. At present, several fluid informations in microchannel that incloud pressure drop, fluid velocity, and fluid mass flow rate were obtained.

The thesis investigates the thermo-mechanical deformation and stress of a flip-chip package (FCBGA) via both experiment and simulation. First, Shadow Moiré is used to evaluate the warpage of a package at elevated temperature. Then we adopt the finite element method incorporated with the software ANSYS to simulate the warpage of a package and compare the obtained results with experiment at data. Then, the material properties of underfill, the thickness of die and the substrate are considered as important parameters. Their effects on stress and strain fields of package are studied. In case of FCBGA with and without underfill, we find that FCBGA with underfill can reduce stress concentration and increase warpage of a package in comparion with FCBGA without underfill. As for FCBGA with and without heat slug, it is observed that the warpage of FCBGA with heat slug is smaller than that of FCBGA without heat slug. Both stress and strain in the packages of above two cases are similar. The parametric study about the underfill, we find that smaller modulus and CTEs of underfill can reduce the stress and strain of package. However in the consideration of thicknesses of both die and substrate, it is shown that thinner die can reduce stress and strain of package, but thinner substrate does not. So it is suggested that thicknesses of die are the thinner the better.

This dissertation focuses on the applications of solid supported phospholipid membranes as mimics of the cellular membrane using lab-on-a-chip devices in order to study biochemical events such as ligand-receptor binding and the chemical mechanism for the preservation of the biomembrane. Supported lipid bilayers (SLBs) mimic the native membrane by presenting the important property of two-dimensional lateral fluidity of the individual lipid molecules within the membrane. This is the same property that allows for the reorganization of native membrane components and facilitates multivalent ligand-receptor interactions akin to immune response, cell signaling, pathogen attack and other biochemical processes. The study is divided into two main facets. The first deals with developing a novel lipopolymer supported membrane biochip consisting of Poly(ethylene glycol) (PEG)-lipopolymer incorporated membranes. The formation and characterization of the lipopolymer membranes was investigated in terms of the polymer size, concentration and molecular conformation. The lateral diffusion of the PEG-bilayers was similar to the control bilayers. The air-stability conferred to SLBs was determined to be more effective when the PEG polymer was at, or above, the onset of the mushroom-to-brush transition. The system is able to function even after dehydration for 24 hours. Ligandreceptor binding was analyzed as a function of PEG density. The PEG-lipopolymer acts as a size exclusion barrier for protein analytes in which the binding of streptavidin was unaffected whereas the binding of the much larger IgG and IgM were either partially or completely inhibited in the presence of PEG. The second area of this study presents a molecular mechanism for in vivo biopreservation by employing solid supported membranes as a model system. The molecular mechanism of how a variety of organisms are preserved during stresses such as anhydrobiosis or cryogenic conditions was investigated. We investigated the interaction of two disaccharides, trehalose and maltose with the SLBs. Trehalose was found to be the most effective in preserving the membrane, whereas maltose exhibited limited protection. Trehalose lowers the lipid phase transition temperature and spectroscopic evidence shows the intercalation of trehalose within the membrane provides the chemical and morphological stability under a stress environment.

The main purpose of this research is to analyze and improve manufacturing process of chip resistor . To startup research by collecting chip resistor related thesises and patents, and as a result, discover most research paper are focused on structure and material, seldom found information related to manufacturing and process. As a matter of fact, manufacturing and process is crucial for mass production. Continued by analyzing chip resistor's structure and manufacture process, use defect sample collected from current manufacturing. Apply functional analysis to explore manufacturing system and environment. Base on analysis on functional structure and the limitation of structure, propose three ways of changing the processing sequence which provide improvement. In one case, after been trail run, it can actually reduce defect of manufacturing and speedup the operation flow. List designing and operating operable of detail stage, according to equipment jig and product dimension explore approach, choose a approach optimum what it raise efficiency and improve defect of chip resistor. Analyze resistance distribution and reliability test after test batch, confirm chip resistor¡¦s function and specification. Analyze defect rate of production ramp-up last. Result of study, provide optimum procedure could be reduce defect rate. Whole process of study, compare defect rate of current and optimum approach, optimum approach could be reduce defect rate from 8.5¢H to 1.3¢H.

The aggressive scaling of the semiconductor technology following the Moore’s Law has delivered true system-on-chip (SoC) integration. Network-on-chip (NoC) has been recently introduced as an effective solution for scalable on-chip communication since dedicated point-to-point (P2P) interconnection and shared bus architecture become performance and power bottlenecks in the SoCs. This dissertation studies three critical NoC challenges such as latency, power, and compatibility with emerging technologies in aspect of an architecture and physical design level. Latency is a key issue in NoC since the performance of applications considerably depends on resource sharing policies employed in an on-chip network. NoCs have been mainly developed to improve network-level performance that captures the inherent performance characteristics of a network itself, but the network-level optimizations are not directly related to application- or system-level performance. In addition, memory latency on NoC critically affects the performance of applications or systems. We propose a synchronous dynamic random access memory (SDRAM) aware NoC design to optimize memory throughput, latency, and design complexity. Furthermore, it is extended to an application-aware NoC design to provide the quality-of-service (QoS) of memory for various applications. NoC provides great on-chip communication. However, it brings no true relief to power budget when the on-chip network scales in terms of complexity/size and signal bandwidth. The combination of NoC and other techniques has the potential to reduce power. We study two power saving research topics for NoC: (a) we propose a voltage-frequency island (VFI) aware NoC optimization framework with a better tradeoff between power efficiency and design complexity to minimize both computation and on-chip communication power. (b) We formulate an application mapping problem to mixed integer quadratic programming (MIQP) with the purpose of reducing power consumption in various hard networks and develop highly efficient algorithms for the MIQP. Regarding NoC compatible with new technologies, we focus on three dimensional (3D) die integration based on through-silicon vias (TSVs). Since an on-chip network design has been subject to not only application constraints but also design/manufacturing constraints, a 3D NoC design is required for innovation in interconnection networks. We propose a chemical-mechanical polishing (CMP) aware application-specific 3D NoC design that minimizes TSV height variation, thus reduces bonding failure, and meanwhile optimizes conventional NoC design objectives such as hop count, wirelength, power, and area. / text

The demands of future computing, as well as the challenges of nanometer-era VLSI design, will require new design techniques and design styles that are simultaneously high performance, energy-efficient, and robust to noise and process variation. One of the emerging problems concerns the communication mechanisms between the increasing number of blocks, or cores, that can be integrated onto a single chip. The bus-based systems and point-to-point interconnection strategies in use today cannot be easily scaled to accommodate the large numbers of cores projected in the near future. Network-on-chip (NoC) interconnect infrastructures are one of the key technologies that will enable the emergence of many-core processors and systems-on-chip with increased computing power and energy efficiency. This dissertation is focused on testing, yield improvement and fault-tolerance of such NoC infrastructures. A fast, efficient test method is developed for NoCs, that exploits their inherent parallelism to reduce the test time by transporting test data on multiple paths and testing multiple NoC components concurrently. The improvement of test time varies, depending on the NoC architecture and test transport protocol, from 2X to 34X, compared to current NoC test methods. This test mechanism is used subsequently to perform detection of NoC link permanent faults, which are then repaired by an on-chip mechanism that replaces the faulty signal lines with fault-free ones, thereby increasing the yield, while maintaining the same wire delay characteristics. The solution described in this dissertation improves significantly the achievable yield of NoC inter-switch channels – from 4% improvement for an 8-bit wide channel, to a 71% improvement for a 128-bit wide channel. The direct benefit is an improved fault-tolerance and increased yield and long-term reliability of NoC based multicore systems.

The scaling of VLSI technology has allowed extensive integration of processing resources on a single chip. Consequently, programmable chips is able to have a high logic and memory capacity for implementation of complex systems. Field-programmable gate arrays (FPGAs) with their embedded memory and other specialized functionality have become viable alternatives in many cases to costly application-specific integrated circuits as a system-on-chip (SoC) substrate. However, on-chip bus-based interconnects are no longer suitable for complex SoC design because of its limited scalability. The network-on-chip (NoC)paradigm has therefore emerged as a scalable approach for addressing this challenge. FPGAs can also adopt the NoC paradigm in order to support more complex SoC implementations. The elements for NoC support can be implemented in conventional programmable logic within an FPGA, however, a dedicated approach for these NoC elements can lead to better performance and more efficient utilization of on-chip FPGA resources. A fixed network topology can be a disadvantage in NoC platforms due to misalignment with application requirements. It is therefore desirable to incorporate a certain level of configurability even for embedded NoC support within an FPGA. This thesis presents the design and implementation of a configurable router intended as a dedicated embedded module for NoC support in an FPGA. The goal is to provide a general NoC infrastructure for the FPGA platform that balances trade-offs with regard to logic complexity, resource utilization, and flexibility. The configurable router provides flexibility in implementing a variety of network topologies with the convenience of a 3-bit input to the router for configuration. All of the necessary routing functionality for each topology is implemented in logic for performance and area efficiency. The overall router design provides general NoC support with reduced complexity, thereby achieving area efficiency and an adequate clock frequency for typical operation in conjunction with embedded soft processors. Synthesis results are presented at the router level in order to characterize the hardware overhead for implementations in programmable logic as well as standard-cell technology, and at the system-level in order to evaluate overall system resource utilization. Operational results are shown at router level to demonstrate correctness and at system level to demonstrate functionality of the multiprocessor systems that utilizes the configurable router. / Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2008-09-24 23:24:01.907

To harness the wealth of success and computational power from the microelectronics industry, lab-on-a-chip (LOAC) applications should be fully integrated with silicon platforms. This works demonstrates a dielectrophoresis-based LOAC device built entirely on silicon using standard CMOS (complementary metal oxide semiconductor) processing techniques. The signal phases on multiple electrodes were controlled with only four electrical contacts, which connected to the device using three metal layers separated with interlayer dielectric. Indium tin oxide was deposited on a milled plastic lid to provide the conductivity and optical clarity necessary to electrically actuate the particles and observe them. The particles and medium were in the microfluidic chamber formed by using conductive glue to bond the plastic milled lid to the patterned silicon substrate. A correlation between the particle velocities and the electric field gradients was made using video microscopy and COMSOL Multiphysics ® simulations.