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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
1

Asymmetric thermal cycles : a different approach to accelerated reliability assessment of microelectronic packages

Classe, Francis Christopher 08 1900 (has links)
No description available.
2

Effect of bonding pressure on reliability of anisotropic conductive adhesives [sic] joints in a silicon-to-flex-substrate interconnction

Puthenparambil, Abhilash. January 2006 (has links)
Thesis (M.S.E.E.)--State University of New York at Binghamton, Watson School of Engineering and Applied Science, 2006. / Includes bibliographical references.
3

Drop impact reliability testing lead-free chip scale packages : a thesis /

Farris, Andrew. Liddicoat, Albert A. January 2008 (has links)
Thesis (M.S.)--California Polytechnic State University, 2008. / Major professor: Albert Liddicoat, Ph.D. "Presented to the faculty of California Polytechnic State University, San Luis Obispo." "In partial fulfillment of the requirements for the degree [of] Master of Science in Electrical Engineering." "June 2008." Includes bibliographical references (leaves 70-73). Also available online. Also available on microfiche (2 sheets).
4

Lead-free assembly and reliability of chip scale packages and 01005 components

Liu, Yueli, Johnson, R. Wayne, January 2006 (has links)
Dissertation (Ph.D.)--Auburn University, / Abstract. Vita. Includes bibliographic references (p.139-147).
5

Damage prediction of lead free ball grid array packages under shock and drop environment

Panchagade, Dhananjay R., January 2007 (has links) (PDF)
Thesis (Ph.D.)--Auburn University, 2007. / Abstract. Vita. Includes bibliographic references (ℓ. 175-)
6

Assembly, reliability, and rework of stacked CSP components

Iyer, Satyanarayan Shivkumar. January 2008 (has links)
Thesis (Ph. D.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Systems Science and Industrial Engineering, 2008. / Includes bibliographical references.
7

Stress Analysis for Chip Scale Packages with Embedded Active Devices under Thermal Cycling

Yeo, Hyunwook 13 June 2014 (has links)
One of the main challenges in the electronics manufacturing and packaging development is how to integrate more functions inside the same or even smaller size. To meet the demand for higher integration, the interest toward passive and active component embedding has been increasing during the past few years. One of the main reasons for the growing interest toward embedded active components, in addition to demand for higher packaging density, is the need for better electrical performance of the component assemblies. However, it is little known how embedded IC and passives affect the reliability of IC packaging. Solder joints have been used in the electronic industry as both structural and electrical interconnections between electronic packages and printed circuit boards (PCB). When solder joints are under thermal cyclic loading, mismatch in coefficients of thermal expansion (CTE) between the printed circuit boards and the solder balls creates thermal strains and stresses on the joints, which may finally result in cracking. Consequently, the mechanical interconnection is lost, leading to electrical failures (such as hard/intermittent open, parametric failure), which in turn causes malfunction of the circuit or whole system. When a die is embedded into a substrate, Young's modulus of the die is larger than one of the core of the substrate and the CTEs of the die is smaller than those of the substrate. As a result, mismatch in coefficients of thermal expansions (CTE) between the substrate with the embedded device and the solder balls may increase. In the present study, the stress of chip scale packages (CSP) with an embedded die under thermal cycling conditions is evaluated using the finite element method. The viscoplastic model for solders including matrix dislocation mechanism and grain boundary sliding model developed by Yi et al. (2002) is employed.
8

Thermo-Mechanical Selective Laser Assisted Die Transfer

Miller, Ross Alan January 2011 (has links)
Laser Induced Forward Transfer (LIFT) techniques show promise as a disruptive technology which will enable the placement of components smaller than what conventional pick-and-place techniques are capable of today. Limitations of current die-attach techniques are presented and discussed and present the opportunity for a new placement method. This study introduces the Thermo-Mechanical Selective Laser Assisted Die Transfer (tmSLADT) process and is an application of the unique blistering behavior of a dynamic releasing layer when irradiated by low energy focused UV laser pulses. The potential of tmSLADT as the next generation LIFT technique is demonstrated by the "touchless" transfer of 65 μm thick silicon tiles between two substrates spaced 195 μm apart. Additionally, the advantages of an enclosed blister-actuator mechanism over previously studied ablative and thermal releasing techniques are discussed. Finally, experimental results studying transfer precision indicate this non optimized die transfer process compares with, and may exceed, the placement precision of current assembly techniques. / Defense Microelectronics Activity (DMEA) under agreement number H94003-09-2-0905

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