In order to carry out the complicated computation inside the high performance computing (HPC) systems, tens to hundreds of parallel processor chips and physical wires are required to be integrated inside the multi-chip package module (MCM). The physical wires considered as the electrical interconnects between the processor chips, however, have the challenges on placements and routings because of the unequal progress between the semiconductor and I/O size reductions. The primary goal of the research is to overcome package design challenges - providing a hybrid computing architecture with implemented 60 GHz antennas as the high efficient wireless interconnect which could generate over 10 Gbps bandwidth on the data transmissions. The dissertation is divided into three major parts. In the first part, two different performance metrics, power loss required to be recovered (PRE) and wireless link budget, on evaluating the antenna's system performance within the chip to chip wireless interconnect are introduced to address the design challenges and define the design goals. The second part contains the design concept, fabrication procedure and measurements of implemented 60 GHz broadband antenna in the application of multi-chip data transmissions. The developed antenna utilizes the periodically-patched artificial magnetic conductor (AMC) structure associated with the ground-shielded conductor in order to enhance the antenna's impedance matching bandwidth. The validation presents that over 10 GHz -10 dB S11 bandwidth which indicates the antenna's operating bandwidth and the horizontal data transmission capability which is required by planar type chip to chip interconnect can be achieved with the design concept. In order to reduce both PRE and wireless link budget numbers, a 60 GHz two-element array in the multi-chip communication is developed in the third part. The third section includes the combined-field analysis, the design concepts on two-element array and feeding circuitry. The simulation results agree with the predicted field analysis and demonstrate the 5dBi gain enhancement in the horizontal direction over a single 60 GHz AMC antenna to further reduce both PRE and wireless link budget numbers.

Low-loss off-chip interconnects are required for energy-efficient communication in dense microprocessors. To meet these needs, air cavity parallel plate and microstrip lines with copper conductors were fabricated on an FR-4 epoxy-fiberglass substrate using conventional microelectronics manufacturing techniques. Copper transmission lines were separated by a composite dielectric of air and Avatrel 2000P and by a dielectric layer of air only. The composite dielectric lines were characterized to 10 GHz while the all air dielectric lines were characterized to 40 GHz. The transmission line structures showed loss as low 1.5 dB/cm at 40 GHz with an effective dielectric constant below 1.4. These novel structures show low loss in the dielectric due to the reduced relative permittivity and loss tangent introduced by the air cavity. Transmission line structures with a composite dielectric were built by coating the sacrificial polymer poly(propylene carbonate) (PPC) over a copper signal line, encapsulating with an overcoat polymer, electroplating a ground line, and decomposing PPC to form an air cavity. The signal and ground wires were separated by a layer of 15 µm of air and 20 µm of Avatrel 2000P. Air cavity formation reduced dielectric constant more than 30 percent and loss of less than 0.5 dB/cm was measured at 10 GHz. Residue from PPC decomposition was observed in the cavity of composite dielectric structures and the decomposition characteristics of PPC were evaluated to characterize the residue and understand its formation. Analysis of PPC decomposition based on molecular weight, molecular backbone structure, photoacid concentration and vapor pressure, casting solvent, and decomposition environment was performed using thermogravimetric analysis and extracting kinetic parameters. Novel interaction of copper and PPC was observed and characterized for the self-patterning of PPC on copper. Copper is dissolved from the surface during PPC spincoating and interacts with the polymer chains to improve stability. The improved thermal stability allows selective patterning of PPC on copper. Decomposition characteristics, residual metals analysis, and diffusion profile were analyzed. The unique interaction could simplify air-gap processing for transmission lines. Inorganic-organic hybrid polymers were characterized for use as overcoat materials. Curing characteristics of the monomers and mechanical properties of the polymer films were analyzed and compared with commercially available overcoat materials. The modulus and hardness of these polymers was too low for use as an air-gap overcoat, but may be valuable as a barrier layer for some applications. The knowledge gained from building transmission line structures with a composite dielectric, analyzing PPC decomposition, interaction with copper, and comparison of hybrid polymers with commercial overcoats was used to build air-gap structures with improved electrical design. The ground metal was separated from the signal only by air. The signal wire was supported from above using 60 µm of Avatrel 8000P as an overcoat. Structures showed loss of less than 1.5 dB/cm at 40 GHz, the lowest reported value for a fully encapsulated transmission line structure.

Dissertation/Thesis / Masters Thesis Electrical Engineering 2015

This thesis presents the design, implementation, and fabrication of an analog front-end (AFE) targeting 2x blind ADC-based receivers. The front-end consists of a combination of an anti-aliasing filter (AAF) and a 2-tap feed-forward equalizer (FFE) (AAF/FFE), the required clock generation circuitry (Ck Gen), 4 time-interleaved 4-b ADCs, and DeMUX. The contributions of this design are the AAF/FFE and the Ck Gen. The overall front-end optimizes the channel/filter characteristics for data-rates of 2-10 Gb/s. The bandwidth of the AAF is scalable with the data-rate and the analog 2-tap feed-forward equalizer (FFE) is designed without the need for noise-sensitive analog delay cells. The test-chip is implemented in 65-nm CMOS and the AAF/FFE occupies 152×86 μm2 and consumes 2.4 mW at 10 Gb/s. Measured frequency responses at data-rates of 10, 5, and 2 Gb/s confirm the scalability of the front-end bandwidth. FFE achieves 11 dB of high-frequency boost at 10 Gb/s.

This thesis presents the design, implementation, and fabrication of an analog front-end (AFE) targeting 2x blind ADC-based receivers. The front-end consists of a combination of an anti-aliasing filter (AAF) and a 2-tap feed-forward equalizer (FFE) (AAF/FFE), the required clock generation circuitry (Ck Gen), 4 time-interleaved 4-b ADCs, and DeMUX. The contributions of this design are the AAF/FFE and the Ck Gen. The overall front-end optimizes the channel/filter characteristics for data-rates of 2-10 Gb/s. The bandwidth of the AAF is scalable with the data-rate and the analog 2-tap feed-forward equalizer (FFE) is designed without the need for noise-sensitive analog delay cells. The test-chip is implemented in 65-nm CMOS and the AAF/FFE occupies 152×86 μm2 and consumes 2.4 mW at 10 Gb/s. Measured frequency responses at data-rates of 10, 5, and 2 Gb/s confirm the scalability of the front-end bandwidth. FFE achieves 11 dB of high-frequency boost at 10 Gb/s.