No description available.

Neutral gas pressure measurements in low Earth orbit (LEO) can facilitate the monitoring of atmospheric gravity waves, which can trigger instabilities that severely disrupt radio frequency communication signals. The Space Neutral Pressure Instrument (SNeuPI) is a low-power instrument detecting neutral gas density in order to determine neutral gas pressure. SNeuPI consists of an ionization chamber and a logarithmic electrometer circuit. The Rev. 1 SNeuPI electrometer prototype does not function as designed. A Rev. 2 electrometer circuit must be designed and its performance characterized across specified operating temperature and input current ranges. This document presents a design topology for the Rev. 2 electrometer and a derivation of the theoretical circuit transfer function. Component selection and layout are discussed. A range of predicted operating input currents is calculated using modeled neutral density data for a range of local times, altitudes, and latitudes corresponding to the conditions expected for the Lower Atmosphere/Ionosphere Coupling Experiment (LAICE) CubeSat mission. Laboratory test setups for measurements performed both under vacuum and at atmospheric pressure are documented in detail. Test procedures are presented to characterize the performance of the Rev. 2 electrometer at a range of controlled operating temperatures. The results of these tests are then extrapolated in order to predict the operation of the circuit at specified temperatures outside of the range controllable under laboratory test conditions. The logarithmic conformance, accuracy, sensitivity, power consumption, and deviations from expected response of the circuit are characterized. The results validate the electrometer for use under its expected flight conditions. / Master of Science

Thesis (PhD)--Stellenbosch University, 2015. / ENGLISH ABSTRACT: In order to facilitate the creation of complex and robust RSFQ digital logic circuits an extensive library of electronic design automation (EDA) tools is a necessity. It is the aim of this work to introduce various methods to improve the current state of EDA in RSFQ circuit design. Firstly, Monte Carlo methods such as Latin Hypercube sampling and Sobol sequences are applied for their variance reduction abilities in approximating circuit yield. In addition, artificial neural networks are also investigated for their applicability in modeling the parameter-yield space. Secondly, a novel technique for circuit functional testing using automated state machine extraction is presented, which greatly simplifies the logical verification of a circuit. This method is also used, along with critical timing extraction, to automatically generate Hardware Description Language(HDL) models which can be used for high level circuit design. Lastly, the Greedy Local search, Simulated Annealing and Genetic Algorithm meta-heuristics were statistically compared in a novel manner using a yield model provided by artificial neural networks. This is done to ascertain their performance in optimising RSFQ circuits in relation to yield. The variance reduction techniques of Latin Hypercube Sampling and Sobol sequences were shown to be beneficial for the use with RSFQ circuits. For optimisation purposes the use of Simulated Annealing and Genetic Algorithms were shown to improve circuit optimisation for possible multi-modal search spaces. An HDL model is also successfully generated from a complex RSFQ circuit for use in high level circuit design which includes critical timing and propagation latency. All the techniques presented in this study form part of a software library that can be further refined and extended in future work.

The objective of the proposed research is to create new reconfigurable RF and millimeter-wave circuit topologies that enable significant systems benefits. The market of RF systems has long evolved under a paradigm where once a system is built, performance cannot be changed. Companies have recognized that building flexibility into RF systems and providing mechanisms to reconfigure the RF performance can enable significant benefits, including: the ability support multiple modulation schemes and standards, the reduction of product size and overdesign, the ability to adapt to environmental conditions, the improvement in spectrum utilization, and the ability to calibrate, characterize, and monitor system performance. This work demonstrates X-band LNA designs with the ability to change the frequency of operation, improve linearity, and digitally control the tradeoff between performance and power dissipation. At W-band frequencies, a novel device configuration is developed, which significantly improves state-of-the-art silicon-based switch performance. The excellent switch performance is leveraged to address major issues in current millimeter-wave systems. A front-end built-in-self-test switch topology is developed to facilitate the characterization of millimeter-wave transceivers without expensive millimeter-wave equipment. A highly integrated Dicke radiometer is also created to enable sensitive measurements of thermal noise.

published_or_final_version / abstract / Electrical and Electronic Engineering / Master / Master of Philosophy

Modern cryptography responds to the need for security that has arisen with the emergence of communication appliances. However, its adapted integration in the wide variety of existing communication systems has opened new design challenges. Amongst them, this thesis addresses two in particular, related to hardware integration of cryptographic algorithms: constrained environments and side-channel security. In the context of constrained environments, we propose to study the interest of the Scalable Encryption Algorithm SEA for constrained hardware applications. We investigate both the FPGA and ASIC contexts and illustrate, using practical implementation results, the interest of this algorithm. Indeed, we demonstrate how hardware implementations can keep its high scalability properties while achieving interesting implementation figures in comparison to conventional algorithms such as the AES. Next, we deal with three complementary aspects related to side-channel resistance. We first propose a new class of dynamic and differential logic families achieving low-power performance with matched leakage of information to state of-the-art countermeasures. We then discuss a power consumption model for these logic styles and apply it to DyCML implementations. It is based on the use of the isomorphism existing between the gate structures of the implemented functions and the binary decision diagrams describing them. Using this model, we are not only able to predict the power consumption, and therefore attack such implementations, but also to efficiently choose the gate structures achieving the best resistance against this model. We finally study a methodology for the security evaluation of cryptographic applications all along their design and test phases. We illustrate the interest of such a methodology at different design steps and with different circuit complexity, using either simulations or power consumption measurements.

"Due to the high variation of critical device parameters inherent in integrated circuit manufacturing, modern integrated circuit designs have evolved to rely on the ratios of similar devices for their performance rather than on the absolute characteristics of any individual device. Today's high performance analog integrated circuits depend on the ability to make identical or matched devices. Circuits are designed using a tolerance based on the overall matching characteristics of their particular manufacturing process. Circuit designers also follow a general rule of thumb that larger devices offer better matching characteristics. This results in circuits that are over designed and circuit layouts that are generally larger than necessary. In this project we develop a model to predict the mismatch in a pair of NPN bipolar transistors. Precise prediction of device mismatch will result in more efficient circuit deigns, smaller circuit layouts and higher test yields, all of which lead to into more reliable and less expensive products."

Ching Ngai-hung. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2001. / Includes bibliographical references (leaves 81-83). / Abstracts in English and Chinese. / Chapter CHAPTER 1 ´ؤ --- INTRODUCTION --- p.1 / Chapter 1.1 --- Background on Micro Power Supply --- p.1 / Chapter 1.2 --- Literature Survey --- p.3 / Chapter 1.2.1 --- Comparison Among Different Power Sources & Transduction Mechanisms --- p.3 / Chapter 1.2.2 --- Previous Works in Vibration Based Generator --- p.6 / Chapter CHAPTER 2 一 --- DESIGN OF THE MICRO-POWER GENERATOR --- p.8 / Chapter 2.1 --- Concept of Power Generation --- p.8 / Chapter 2.2 --- Design Objectives of the Micro Power Generation --- p.9 / Chapter 2.3 --- System Modelling and Configuration of the Generator --- p.10 / Chapter 2.4 --- RESONATING STRUCTURE --- p.13 / Chapter 2.4.1 --- Material Selection --- p.13 / Chapter 2.4.2 --- Fabrication Method --- p.14 / Chapter CHAPTER 3 一 --- INDUCTING STRUCTURE --- p.17 / Chapter 3.1 --- Selection of Winding Method --- p.17 / Chapter 3.2 --- Solenoid Windings --- p.19 / Chapter 3.2.1 --- Fabrication Process --- p.19 / Chapter 3.3 --- PCB Windings --- p.20 / Chapter 3.3.1 --- Fabrication Process of the Prototype of Six-layer PCB --- p.21 / Chapter CHAPTER 4 一 --- EXPERIMENTAL RESULTS --- p.27 / Chapter 4.1 --- Experimental Setup --- p.27 / Chapter 4.1.1 --- Generator Systems --- p.27 / Chapter 4.1.2 --- Measurement of Vibration and Output from the Generator --- p.28 / Chapter 4.1.3 --- Observations of Vibration Motions --- p.31 / Chapter 4.2 --- SPRING FOR THE MICRO GENERATOR --- p.32 / Chapter 4.2.1 --- Spring Micromachining Optimization --- p.32 / Chapter 4.2.2 --- Mode Shapes and Spiral-spring Structures --- p.35 / Chapter 4.3 --- MAGNET FOR THE MICRO GENEARTOR --- p.37 / Chapter 4.3.1 --- Generator Output and Magnetic Dipole Orientation --- p.37 / Chapter 4.4 --- HAND-WIRED COIL GENEARTOR --- p.45 / Chapter 4.4.1 --- Performance of Different Design of Housings --- p.45 / Chapter 4.5 --- PCB COIL GENERATOR --- p.48 / Chapter 4.5.1 --- Size of PCB Coils vs. Generator Output --- p.48 / Chapter 4.5.2 --- Effect of Number of PCB Layers --- p.54 / Chapter 4.5.3 --- Array of Generators --- p.61 / Chapter CHAPTER 5 一 --- MODELLING AND COMPUTER SIMULATION --- p.63 / Chapter 5.1 --- Modelling the Second-Order System --- p.63 / Chapter CHAPTER 6 一 --- APPLICATION DEMONSTRATIONS --- p.69 / Chapter 6.1 --- INFRARED SIGNAL TRANSMISSION --- p.69 / Chapter 6.2 --- RF WIRELESS TEMPERATURE SENSING SYSTEM --- p.70 / Chapter CHAPTER 7 ´ؤ --- CONCLUSION --- p.75 / Chapter CHAPTER 8 一 --- FUTURE WORK --- p.77 / BIBLIOGRAPHY --- p.81 / APPENDIX --- p.84

Advances in semiconductor technology and design automation methods have introduced a new era for electronic products. With design sizes in millions of logic gates and operating frequencies in GHz, defects-per-million rates continue to increase, and defects are manifesting themselves in subtle ways. / Diagnosing functional failures in complicated electronic boards is a challenging task, wherein debug technicians try to identify defective components by analyzing some syndromes obtained from the application of diagnostic tests. The diagnosis effectiveness and efficiency rely heavily on the quality of the in-house developed diagnostic tests and the debug technicians’ knowledge and experience, which, however, have no guarantees nowadays. To tackle this problem, this thesis proposes a novel agent-assisted diagnostic framework for board-level functional failures, namely AgentDiag, which facilitates to evaluate the quality of the diagnostic tests and bridge the knowledge gap between the diagnostic programmers who write diagnostic tests and the debug technicians who conduct in-field diagnosis with a lightweight model of the boards and tests. / Machine learning algorithms have been advocated for automated diagnosis of board-level functional failures due to the extreme complexity of the problem. Such reasoning-based solutions, however, remain ineffective at the early stage of the product cycle, simply because there are insufficient historical data for training the diagnostic system that has a large number of test syndromes. Guided by a proposed metric isolation capability, AgentDiag is able to leverage the knowledge from the lightweight model to selecting a reduced test syndrome set for diagnosis in an adaptive manner. / While AgentDiag is effective to improve the diagnostic accuracy, this technique, by excluding some test syndromes, may cause information loss for diagnosis. The thesis further presents a novel test syndrome merging methodology to address this problem. That is, by leveraging the domain knowledge of the diagnostic tests and the board structural information, we adaptively reduce the feature size of the diagnostic system by selectively merging test syndromes such that it can effectively utilize the available training cases. / Experimental results on real industrial boards and an OpenRISC design demonstrate the effectiveness of the proposed solutions. / 半導體技術和設計自動化的高速發展開啟了電子產品的新紀元。百萬級別的設計尺寸和上G赫茲的操作頻率使得每百萬次採樣數的缺陷率繼續上升，缺陷顯現方式也日益微妙。 / 複雜電子板的診斷是一項極具挑戰的工作。調試人員通常通過分析診斷測試所產生的症狀，甄別有缺陷的元件。診斷的有效性和效率就極大地依賴於診斷測試的質量和調試人員的知識經驗，但是現在這些都是沒有確定性的。為了解決這一問題，本文提出一個新穎的針對板級功能性故障的代理輔助診斷系統AgentDiag。它幫助評估診斷測試的質量，並架起編寫診斷測試的測試程式員和從事實際診斷工作的調試人員之間的橋樑。 / 因為板級診斷的極度複雜，機器學習算法已經被提出來解決這一問題。但是這些基於推導的方法在早期很難達到好的效果，原因是過大的測試數量和相對較少的訓練數據。在度量Isolation Capability的引導下，能夠適應性地利用來自輕量級模型的知識去選取一個症狀集進行診斷。 / AgentDiag可以有效地提高診斷準確率，但是由於是直接剔除一部分測試症狀，所以有可能造成信息的丟失。本文進一步提出了一個測試症狀合併的方法來解決這一問題。那就是利用診斷測試和電路板的結構描述，我們可以適應性地利用選擇性合併的測試症狀來減少測試症狀的數目，從而有效地利用已有的測試數據。 / 來自實際的工業電路板和OpenRisc設計的實驗數據驗證了提出的方法的有效性。 / Sun, Zelong. / Thesis M.Phil. Chinese University of Hong Kong 2014. / Includes bibliographical references (leaves 47-51). / Abstracts also in Chinese. / Title from PDF title page (viewed on 12, October, 2016). / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only.

The growing interest in programmable analog circuits has led to the development of Field Programmable Analog Arrays (FPAAs). An FPAA consists of: 1) a programmable cell that can be reconfigured to perform several analog functions. 2) an architecture that interconnects a number of copies of the programmable cell. In this thesis, the full monolithic circuit implementation of the analog part of the programmable cell is presented. Chapter I gives an introduction to the idea of FPAA and introduces the FPAA architecture and the cell block diagram. Chapter II deals with the design and verification of a differential current-mode four-quadrant multiplier. The weighting-summing circuit with the normalizing stage is discussed in Chapter III. Chapter IV presents the design of a current-mode low-voltage programmable integratorgain circuit. Programmability was achieved by changing the bias current in the designed circuits; no analog switches were used in the signal path. This shows no effect on the performance of the circuits. The presented programming method, however, relies on the availability of a programmable current source with a storage capability. The design of this current source is discussed in chapter V. Conclusions are summarized in Chapter VI. The presented designs throughout the whole thesis were supported by detailed analytical derivations with the necessary SPICE simulations to verify the performance.