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In developing a compact electro-optic sampling system for industrial use it is desirable to utilize a semiconductor laser diode as the light source since these devices are compact and economical. This thesis investigates several novel laser driver techniques for generating extremely short optical gain switched pulses from a semiconductor laser diode. These techniques include a novel bias control scheme in which the bias to a semiconductor laser diode, that is being driven with a step recovery diode pulse generator circuit, is turned on and off in order to switch the gain switched optical pulses on and off as desired. The second technique involves a mono-cycle scheme that allows a step recovery diode pulse generator circuit, which is customarily driven by a fixed frequency oscillator, to be driven by a mono-cycle pulse train of variable repetition rate. An equivalent circuit model of a laser diode based on the mono-mode rate equations is discussed and implemented in SPICE for the purpose of studying the interaction of the laser driver circuit electronics and the laser diode. The laser diode equivalent circuit is benchmarked against analytical solutions of the rate equations. A qualitative agreement between the measurements of the laser diode optical and terminal voltage responses and the SPICE simulations of the laser diode equivalent circuit model are demonstrated. / Thesis / Master of Engineering (ME)

Modeling of wind farms to determine their short circuit contribution in response to faults is a crucial part of system impact studies performed by power utilities. Short circuit calculations are necessary to determine protective relay settings, equipment ratings and to provide data for protection coordination. The plethora of different factors that influence the response of wind farms to short circuits makes short circuit modeling of wind farms an interesting, complex, and challenging task. Low voltage ride through (LVRT) requirements make it necessary for the latest generation of wind generators to be capable of providing reactive power support without disconnecting from the grid during and after voltage sags. If the wind generator must stay connected to the grid, a facility has to be provided to by-pass the high rotor current that occurs during voltage sags and prevent damage of the rotor side power electronic circuits. This is done through crowbar circuits which are of two types, namely active and passive crowbars, based on the power electronic device used in the crowbar triggering circuit. Power electronics-based converters and controls have become an integral part of wind generator systems like the Type 3 doubly fed induction generator based wind generators. The proprietary nature of the design of these power electronics makes it difficult to obtain the necessary information from the manufacturer to model them accurately. Also, the use of power electronic controllers has led to phenomena such as sub-synchronous control interactions (SSCI) in series compensated Type 3 wind farms which are characterized by non-fundamental frequency oscillations. SSCI affects fault current magnitude significantly and is a crucial factor that cannot be ignored while modeling series compensated Type 3 wind farms. These factors have led to disagreement and inconsistencies about which techniques are appropriate for short circuit modeling of wind farms. Fundamental frequency models like voltage behind transient reactance model are incapable of representing the majority of critical wind generator fault characteristics such as sub-synchronous interactions. The Detailed time domain models, though accurate, demand high levels of computation and modeling expertise. Voltage dependent current source modeling based on look up tables are not stand-alone models and provide only a black-box type of solution. The short circuit modeling methodology developed in this research work for representing a series compensated Type 3 wind farm is based on the generalized averaging theory, where the system variables are represented as time varying Fourier coefficients known as dynamic phasors. The modeling technique is also known as dynamic phasor modeling. The Type 3 wind generator has become the most popular type of wind generator, making it an ideal candidate for such a modeling method to be developed. The dynamic phasor model provides a generic model and achieves a middle ground between the conventional electromechanical models and the cumbersome electromagnetic time domain models. The essence of this scheme to model a periodically driven system, such as power converter circuits, is to retain only particular Fourier coefficients based on the behavior of interest of the system under study making it computationally efficient and inclusive of the required frequency components, even if non-fundamental in nature. The capability to model non-fundamental frequency components is critical for representing sub-synchronous interactions. A 450 MW Type 3 wind farm consisting of 150 generator units was modeled using the proposed approach. The method is shown to be highly accurate for representing faults at the point of interconnection of the wind farm to the grid for balanced and unbalanced faults as well as for non-fundamental frequency components present in fault currents during sub-synchronous interactions. Further, the model is shown to be accurate also for different degrees of transmission line compensation and different transformer configurations used in the test system.

One of the major tasks in electronic circuit design is the ability to predict the performance of general circuits in the presence of uncertainty in key design parameters. In the mathematical literature, such a task is referred to as uncertainty quantification. Uncertainty about the key design parameters arises mainly from the difficulty of controlling the physical or geometrical features of the underlying design, especially at the nanometer level. With the constant trend to scale down the process feature size, uncertainty quantification becomes crucial in shortening the design time. To achieve the uncertainty quantification, this thesis presents a new approach based on the concept of generalized Polynomial Chaos (gPC) to perform variability analysis of general nonlinear circuits. The proposed approach is built upon a decoupling formulation of the Galerkin projection (GP) technique, where the large matrix is transformed into a block-diagonal whose diagonal blocks can be factorized independently. The proposed methodology provides a general framework for decoupling the GP formulation based on a general system of orthogonal polynomials. Moreover, it provides a new insight into the error level that is caused by the decoupling procedure, enabling an assessment of the performance of a wide variety of orthogonal polynomials. For example, it is shown that, for the same order, the Chebyshev polynomials outperforms other commonly used gPC polynomials.

Im Rahmen der vorliegenden Arbeit wird die Kompaktier-Granulierung von Kalisalzen zur Herstellung von Düngemittelgranulat experimentell untersucht und ein Modellansatz zur Beschreibung von derartigen Kreisläufen abgeleitet. Bei der Kompaktier-Granulierung wird fein-disperses Kalisalz mit Hilfe von Walzenpressen zu sogenannten Schülpen verpresst. Diese werden durch nachfolgende Zerkleinerung und Klassierung zu Düngemittelgranulat (enge Partikelgrößenklasse, wie beispielsweise 2 – 4 mm) verarbeitet. Basierend auf halb-industriellen Kreisläufen werden im vorliegenden Beitrag wesentliche Prozesswechselwirkungen zwischen Kompaktierung, Zerkleinerung und Klassierung ausgearbeitet. Detailuntersuchungen zeigen, dass sich insbesondere die Schülpenfestigkeiten wie auch die schüttgutmechanischen Eigenschaften des Pressenaufgabegutes im Kreislaufbetrieb ändern. Darauf aufbauend wird ein Modellansatz abgeleitet der die Abschätzung des Kreislaufbetriebs erlaubt.

Network-on-chip (NoC) based multi-processor systems-on-chip (MPSoCs) are promising candidates for future multi-processor embedded platforms, which are expected to be composed of hundreds of heterogeneous processing elements (PEs) to potentially provide high performances. However, together with the performances, the systems complexity will increase, and new high level design techniques will be needed to efficiently model, simulate, debug and synthesize them. System-level design (SLD) is considered to be the next frontier in electronic design automation (EDA). It enables the description of embedded systems in terms of abstract functions and interconnected blocks. A promising complementary approach to SLD is the use of models of computation (MoCs) to formally describe the execution semantics of functions and blocks through a set of rules. However, also when this formalization is used, there is no clear way to synthesize system-level models into software (SW) and hardware (HW) towards a NoC-based MPSoC implementation, i.e., there is a lack of system design automation (SDA) techniques to rapidly synthesize and prototype system-level models onto heterogeneous NoC-based MPSoCs. In addition, many of the proposed solutions require large overhead in terms of SW components and memory requirements, resulting in complex and customized multi-processor platforms. In order to tackle the problem, a novel model-based SDA flow has been developed as part of the thesis. It starts from a system-level specification, where functions execute according to the synchronous MoC, and then it can rapidly prototype the system onto an FPGA configured as an heterogeneous NoC-based MPSoC. In the first part of the thesis the HeartBeat model is proposed as a model-based technique which fills the abstraction gap between the abstract system-level representation and its implementation on the multiprocessor prototype. Then details are provided to describe how this technique is automated to rapidly prototype the modeled system on a flexible platform, permitting to adjust the system specification until the designer is satisfied with the results. Finally, the proposed SDA technique is improved defining a methodology to automatically explore possible design alternatives for the modeled system to be implemented on a heterogeneous NoC-based MPSoC. The goal of the exploration is to find an implementation satisfying the designer's requirements, which can be integrated in the proposed SDA flow. Through the proposed SDA flow, the designer is relieved from implementation details and the design time of systems targeting heterogeneous NoC-based MPSoCs on FPGA is significantly reduced. In addition, it reduces possible design errors proposing a completely automated technique for fast prototyping. Compared to other SDA flows, the proposed technique targets a bare-metal solution, avoiding the use of an operating system (OS). This reduces the memory requirements on the FPGA platform comparing to related work targeting MPSoC on FPGA. At the same time, the performance (throughput) of the modeled applications can be increased when the number of processors of the target platform is increased. This is shown through a wide set of case studies implemented on FPGA. / <p>QC 20140609</p>