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<p> This thesis focuses on the noise model verification at both device and circuit levels using circuit simulators. The techniques and procedures developed in this thesis are general and can be applied to any proposed RF noise model equations. To fulfil the two tasks, three main topics have been accomplished. First, a general noise source implementation method has been presented in detail in this thesis and is verified with measurements for both long and short-channel MOSFETs. This method provides a simple and effective way to implement the enhanced channel noise and induced gate noise of MOSFETs without increasing the simulation complexity for the simulators.</p> <p> Second, a systematic procedure to refine the model parameters used in noise calculation is presented. For a model to accurately predict the HF noise characteristics, the accuracy in the prediction of both DC and AC characteristics has to be ensured. The procedure proposed in this thesis provides both DC and AC model parameter verification and optimization for RF noise simulation purpose.</p> <p> Third, as for benchmark circuits to verify noise model at the circuit level, two LNA designs are proposed in the thesis. The first design gives the emphasis on the noise reduction technique and the LNA design procedure. The proposed noise reduction technique gives circuit designers more control on noise figure minimization through noise matching. The second design is used to experimentally verify the noise model at the circuit level.</p> / Thesis / Master of Applied Science (MASc)

The problem of modeling systems from frequency response measurements is of interest to many engineers. In electronics, we wish to construct a macromodel from tabulated impedance, admittance or scattering parameters to incorporate it into a circuit simulator for performing circuit analyses. Structural engineers employ frequency response functions to determine the natural frequencies and damping coefficients of the underlying structure. Subspace identification, popular among control engineers, and vector fitting, used by electronics engineers, are examples of algorithms developed for this problem. This thesis has three goals. 1. For multi-port devices, currently available algorithms arc expensive. This thesis therefore proposes an approach based on the Loewner matrix pencil constructed in the context of tangential interpolation with several possible implementations. They are fast, accurate, build low dimensional models, and are especially designed for a large number of terminals. For noise-free data, they identify the underlying system, rather than merely fitting the measurements. For noisy data, their performance is analyzed for different noise levels introduced in the measurements and an improved version, which identifies an approximation of the original system even for large noise values, is proposed. 2. This thesis addresses the problem of generating parametric models from measurements performed with respect to the frequency, but also with respect to one or more design parameters, which could relate to geometry or material properties. These models are suited for performing optimization over the design variables. The proposed approach generalizes the Loewner matrix to data depending on two variables. 3. This thesis analyzes the convergence properties of vector fitting, an iterative algorithm that relocates the poles of the model, given some "starting poles" chosen heuristically. It was recognized as a reformulation of the Sanathanan-Koerner iteration and several authors attempted to improve its convergence properties, but a thorough convergence analysis has been missing. Numerical examples show that for high signal to noise ratios, the iteration is convergent, while for low ones, it may diverge. Hence, incorporating a Newton step aims at making the iteration always convergent for "starting poles" chosen close to the solution. A connection between vector fitting and the Loewner framework is exhibited, which resolves the issue of choosing the starting poles.

This project focuses on a prototype system architecture which integrates features of an event-driven gate-level simulator and features of the multiple expert system architecture, HEARSAY-II. Combining artificial intelligence and simulation techniques, a knowledge-based simulator was designed and constructed to model non-standard circuit behavior. This non-standard circuit behavior is amplified by advances in integrated circuit technology. Currently available digital circuit simulators can not simulate this behavior. Circuit designer expertise on behavioral phenomena is used in the expert system to guide the base simulator by manipulating its events to achieve the desired behavior.

Thin Film Transistors (TFTs) are widely used in large area electronics because they offer the advantage of low cost fabrication and wide substrate choice. TFTs have been conventionally used for switching applications in large area display arrays. But when it comes to designing a sensor actuator system on a flexible substrate comprising entirely of organic and inorganic TFTs, there are two main challenges – i) Fabrication of complementary TFT devices is difficult ii) TFTs have a drift in their threshold voltage (VT) on application of gate bias. Also currently there are no circuit simulators in the market which account for the effect of VT drift with time in TFT circuits. The first part of this thesis focuses on integrating the VT shift model in the commercially available AIM-Spice circuit simulator. This provides a new and powerful tool that would predict the effect of VT shift on nodal voltages and currents in circuits and also on parameters like small signal gain, bandwidth, hysteresis etc. Since the existing amorphous silicon TFT models (level 11 and level 15) of AIM-Spice are copyright protected, the open source BSIM4V4 model for the purpose of demonstration is used. The simulator is discussed in detail and an algorithm for integration is provided which is then supported by the data from the simulation plots and experimental results for popular TFT configurations. The second part of the thesis illustrates the idea of using negative feedback achieved via contact resistance modulation to minimize the effect of VT shift in the drain current of the TFT. Analytical expressions are derived for the exact value of resistance needed to compensate for the VT shift entirely. Circuit to realize this resistance using TFTs is also provided. All these are experimentally verified using fabricated organic P-type Copper Phthalocyanine (CuPc) and inorganic N-type Tin doped Zinc Oxide (ZTO) TFTs. The third part of the thesis focuses on building a robust amplifier using these TFTs which has time invariant DC voltage level and small signal gain at the output. A differential amplifier using ZTO TFTs has been built and is shown to fit all these criteria. Ideas on vertical routing in an actual sensor actuator interface using this amplifier have also been discussed such that the whole system may be “tearable” in any contour. Such a sensor actuator interface can have varied applications including wrap around thermometers and X-ray machines.