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Baud-rate clock recovery (CR) is gradually gaining popularity in modern serial data transmission systems since these CR techniques do not require edge-samples for extracting timing information. However, previous baud-rate techniques for high-speed serial links either rely on specific 4-bit patterns or uncorrelated random data. This work describes the modeling and design of analog filter front-end aided baud-rate CR schemes. Unlike other baud-rate schemes, this technique is not constrained by the properties of the input random data. Firstly, the thesis develops a hardware-efficient baud-rate algorithm that requires only the slope information of the incoming random data. Called modified sign-sign minimum mean squared error (SSMMSE), this algorithm adjusts the clock sampling phase until the slope is zero through a bang-bang control loop. Secondly, the performance of a modified SSMMSE phase detector is investigated and compared with a conventional edge-sampled phase detector. It is shown that, at severe noise levels, the proposed modified SSMMSE method has better performance compared to the edge-sampled method for equal loop bandwidths.Thirdly, the thesis investigates different hardware-efficient slope detection techniques. Both passive and active filter based slope detection techniques are demonstrated in this work. In addition to slope generation, the active filter performs linear equalization as well. However, the passive filter generates the slope information at higher speeds than the active filter and also consumes less power. The two filters are used to recover a 2-GHz clock by using an external bang-bang loop. In short, the thesis demonstrates that area and power savings can be achieved by utilizing slope information from front-end filters without compromising the performance of the CR unit.

Lai Cheung Fai. / Cover title. / Thesis (M.B.A.)--Chinese University of Hong Kong. / Bibliography: leaves 110-111.

In ultra-deep submicron VLSI designs, clock network layout plays an increasingly important role in determining circuit performance including timing, power consumption, cost, power supply noise and tolerance to process variations. It is required that a clock layout algorithm can achieve any prescribed skews with the minimum wire length and acceptable slew rate. Traditional zero-skew clock routing methods are not adequate to address this demand, since they tend to yield excessive wire length for prescribed skew targets. The interactions among skew targets, sink location proximities and capacitive load balance are analyzed. Based on this analysis, a maximum delay-target ordering merging scheme is suggested to minimize wire and buffer area, which results in lesser cost, power consumption and vulnerability to process variations. During the clock routing, buffers are inserted simultaneously to facilitate a proper slew rate level and reduce wire snaking. The proposed algorithm is simple and fast for practical applications. Experimental results on benchmark circuits show that the algorithm can reduce the total wire and buffer capacitance by 60% over an extension of the existing zero-skew routing method.

As VLSI technology moves into the Ultra-Deep Sub-Micron (UDSM) era, manufacturing variations, power supply noise and temperature variations greatly affect the performance and yield of VLSI circuits. Clock Distribution Network (CDN), which is one of the biggest and most important nets in any synchronous VLSI chip, is especially sensitive to these variations. To address this problem variability-aware analysis and optimization techniques for VLSI circuits are needed. In the first part of this thesis an analytical bound for the unwanted skew due to interconnect variation is established. Experimental results show that this bound is safer, tighter and computationally faster than existing approaches. This bound could be used in variation-aware clock tree synthesis.The second part of the thesis deals with optimizing a given clock tree to minimize the unwanted skew variations. Non-tree CDNs have been recognized as a promising approach to overcome the variation problem. We propose a novel non-tree CDN obtained by adding cross links in an existing clock tree. We analyze the effect of the link insertion on clock skew variability and propose link insertion schemes. The non-tree CDNs so obtained are shown to be highly tolerant to skew variability with very little increase in total wire-length. This can be used in applications such as ASIC design where a significant increase in the total wire-length is unacceptable.

Recent years have seen a tremendous growth in the development of small sensing devices capable of data processing and wireless communication through their embed- ded processors and radios. Wireless Sensor Networks (WSNs) are ad hoc networks consisting of such devices gaining importance due to their emerging applications. For a meaningful processing of the information sensed by WSN nodes, the clocks of these individual nodes need to be matched through some well de¯ned procedures. This dissertation focuses on deriving e±cient estimators for the clock parameters of the network nodes for synchronization with the reference node and the estimators variance thresholds are obtained to lower bound the maximum achievable performance. For any general time synchronization protocol involving a two way message ex- change mechanism, the BLUE-OS and the MVUE of the clock o®set between them is derived assuming both symmetric and asymmetric exponential network delays. Next, with the inclusion of clock skew in the model, the joint MLE of clock o®set and skew under both the Gaussian and the exponential delay model and the corresponding al- gorithms for ¯nding these estimates are presented. Also, for applications where even clock skew correction cannot maintain long-term clock synchronization, a closed-form expression for the joint MLE for a quadratic model is obtained. Although the derived MLEs are not computationally very complex, two compu- tationally e±cient algorithms have been proposed to estimate the clock o®set and skew regardless of the distribution of the delays. Afterwards, extending the idea of having inactive nodes in a WSN overhear the two-way timing message communication between two active (master and slave) nodes, the MLE, the BLUE-OS, the MVUE and the MMSE estimators for the clock o®sets of the inactive nodes located within the communication range of the active nodes are derived, hence synchronizing with the reference node at a reduced cost. Finally, focusing on the the one-way timing exchange mechanism, the joint MLE for clock phase o®set and skew under exponential noise model and the Gibbs Sampler for a receiver-receiver protocol is formulated and found via a direct algorithm. Lower and upper bounds for the MSE of JMLE and Gibbs Sampler are introduced in terms of the MSEs of the MVUE and the conventional BLUE, respectively.

Unicellular freshwater cyanobacterium Synechococcus elongatus PCC 7942 is the model organism for studying the circadian clock in cyanobacteria. Despite tremendous work over the last decade in identification of clock-related loci and elucidation of molecular mechanisms of the central oscillator, many details of the basic steps in generating circadian rhythms of biological processes remain unsolved and many components are still missing. A transposon-mediated mutagenesis and sequencing strategy has been adopted to disrupt essentially every locus in the genome so as to identify all of the loci that are involved in clock function. The complete genome sequence has been determined by a combination of shotgun sequences and transposon-mediated sequences. The S. elongatus PCC 7942 genome is 2,695,903 bp in length, and has a 55.5% GC content. Automated annotation identified 2,856 protein-coding genes and 51 RNA coding loci. A system for community refinement of the annotation was established. Organization and characteristic features of the genome are discussed in this dissertation. More than 95% of the PCC 7942 genome has been mutagenized and mutants affected in approximately 30% of loci have been screened for defects in circadian function. Approximately 70 new clock loci that belong to different functional categories have been discovered through a team effort. Additionally, functional analysis of insertion mutants revealed that the Type-IV pilus assembly protein PilN and the RNA chaperon Hfq are involved in transformation competence of S. elongatus cells. Functional analysis of an atypical short period kaiA insertional mutant showed that the short period phenotype is caused mainly by the truncation of KaiA by three amino acid residues. The interaction between KaiC and the truncated KaiA is weakened as shown by fluorescence anisotropy analysis. Deletion analysis of pANL, the large endogenous plasmid, implies that two toxin-antitoxin cassettes were responsible for inability to cure cells of this plasmid. In summary, the results indicate that this functional genomics project is very promising toward fulfilling our goal to assemble a comprehensive view of the cyanobacterial circadian clock. The mutagenesis reagents and dataset generated in this project will also benefit the greater scientific community.

As VLSI technology moves into the Ultra-Deep Sub-Micron (UDSM) era, manufacturing variations, power supply noise and temperature variations greatly affect the performance and yield of VLSI circuits. Clock Distribution Network (CDN), which is one of the biggest and most important nets in any synchronous VLSI chip, is especially sensitive to these variations. To address this problem variability-aware analysis and optimization techniques for VLSI circuits are needed. In the first part of this thesis an analytical bound for the unwanted skew due to interconnect variation is established. Experimental results show that this bound is safer, tighter and computationally faster than existing approaches. This bound could be used in variation-aware clock tree synthesis.The second part of the thesis deals with optimizing a given clock tree to minimize the unwanted skew variations. Non-tree CDNs have been recognized as a promising approach to overcome the variation problem. We propose a novel non-tree CDN obtained by adding cross links in an existing clock tree. We analyze the effect of the link insertion on clock skew variability and propose link insertion schemes. The non-tree CDNs so obtained are shown to be highly tolerant to skew variability with very little increase in total wire-length. This can be used in applications such as ASIC design where a significant increase in the total wire-length is unacceptable.

In ultra-deep submicron VLSI designs, clock network layout plays an increasingly important role in determining circuit performance including timing, power consumption, cost, power supply noise and tolerance to process variations. It is required that a clock layout algorithm can achieve any prescribed skews with the minimum wire length and acceptable slew rate. Traditional zero-skew clock routing methods are not adequate to address this demand, since they tend to yield excessive wire length for prescribed skew targets. The interactions among skew targets, sink location proximities and capacitive load balance are analyzed. Based on this analysis, a maximum delay-target ordering merging scheme is suggested to minimize wire and buffer area, which results in lesser cost, power consumption and vulnerability to process variations. During the clock routing, buffers are inserted simultaneously to facilitate a proper slew rate level and reduce wire snaking. The proposed algorithm is simple and fast for practical applications. Experimental results on benchmark circuits show that the algorithm can reduce the total wire and buffer capacitance by 60% over an extension of the existing zero-skew routing method.

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