Demand for low cost Serializer and De-serializer (SerDes) integrated circuits has increased due to the widespread use of Synchronous Optical Network (SONET)/Gigabit Ethernet network and chip-to-chip interfaces such as PCI-Express (PCIe), Serial ATA(SATA) and Fibre channel standard applications. Among all these applications, clock data recovery (CDR) is one of the key design components. With the increasing demand for higher bandwidth and high integration, Complementary metal-oxidesemiconductor (CMOS) implementation is now a design trend for the predominant products. In this research work, a fully integrated 10Gb/s (OC-192) CDR architecture in standard 0.18 μ m CMOS is developed. The proposed architecture integrates the typically large off-chip filter capacitor by using two feed-forward paths configuration to generate the required zero and poles and satisfies SONET jitter requirements with a total power dissipation (including the buffers) of 290mW. The chip exceeds SONET OC-192 jitter tolerance mask, and high frequency jitter tolerance is over 0.31 UIpp by applying PRBS data with a pattern length of 231-1.The implementation is the first fully integrated 10Gb/s CDR IC which meets/exceeds the SONET standard in the literature. The second proposed CDR architecture includes an adaptive bang-bang control algorithm. For 6MHz sinusoidal jitter modulation, the new architecture reduces the tracking error to 11.4ps peak-to-peak, versus that of 19.7ps of the conventional bangbang CDR. The main contribution of the proposed architecture is that it optimizes the loop dynamics by adjusting the bang-bang bandwidth adaptively to minimize the steady state jitter of the CDR, which leads to an improved jitter tolerance performance. According to simulation, the jitter performance is improved by more than 0.04UI,which alleviates the stringent 0.1UI peak to peak jitter requirements in the PCIe/Fibre channel/Sonet Standard.

The genetic identification of molecular mechanisms responsible for circadian rhythm generation has advanced tremendously over the past 25 years. However the molecular identities of the avian clock remain largely unexplored. The present studies seek to determine candidate clock components in the avian species Gallus domesticus. Construction and examination of the transcriptional profiles of the pineal gland and retina using DNA microarray analysis provided a clear view into the avian clock mechanism. Investigation of the pineal and retina transcriptomes determined the mRNA profiles of several thousand genes over the course of one day in LD (daily) and one day in DD (circadian) conditions. Several avian orthologs of mammalian clock genes were identified and many exhibited oscillating patterns of mRNA abundance including several of the putative avian clock genes. Comparison of the pineal transcriptional profile to that of the retina revealed several intriguing candidate genes that may function as core clock components. Including the putative avian clock genes and several others implicated in phototransduction, metabolism, and immune response. A more detailed examination of several candidate photoisomerase/photopigment genes identified from our transcriptional profiling was conducted. These include peropsin (rrh), RGR-opsin (rgr), melanopsin (opn4) and cryptochrome 2 (cry2) genes. This analysis revealed several interesting patterns of mRNA distribution and regulation for these genes in the chick. First, the mRNA of all 4 genes is located within the Inner Nuclear Layer (INL) and Retinal Ganglion cell Layers (RGL) of the ocular retina, where circadian photoreception is present. Second, opn4 and cry2 mRNA is expressed in the photoreceptor layer of the chick retina where melatonin biosynthesis occurs. Lastly, the mRNA for all 4 candidate photopigment genes is regulated on a circadian basis in the pineal gland. As a whole these data yield significant insight into the mechanisms of the avian circadian system and present several candidate genes that may function to integrate photic information, and/or regulate circadian rhythm generation in birds.

Thanks to the booming of car electronics in recent years, more car electronics devices are installed in ve-hicles. These devices are connected by in-vehicle communication networks. In this thesis, we present the tran-sceiver and clock generator design for the physical layer of a FlexRay-based in-vehicle communication protocol. Regarding the transceiver design, a LVDS-like transmitter is proposed to drive the twisted pair of the bus. By contrast, a 3-comparator scheme is used to carry out the required bit-slicing and state recognition at the re-ceiver end. The reliability and safety are the priority design factors for electronics. A robust 20 MHz clock generator with process, supply voltage, and temperature compensation, a sub-1 MHz oscillator, and a temperature detector are included in our clock generator design. All of these designs are implemented by using a typical 0.18 um single-poly six-metal CMOS process. The proposed prototypical transceiver has been tested by a thermo chamber to justify its operation in the required temperature rage, i.e., -40¢XC to 125¢XC. Moreover, the compatibility of our design is also verified in a real FlexRay-based network. The maximum throughput of the proposed prototypical transceiver can reach 40 Mbps.

As VLSI fabrication technology scales, an increasing number of processing elements (cores) on a chip makes on-chip communication a new performance bottleneck. The Network-on-Chip (NoC) paradigm has emerged as an efficient and scalable infrastructure to handle the communication needs for such multi-core systems. In most existing NoCs, design decisions are made assuming that the NoC operates at the same or lower clock speed as the cores, which slows down the communication system. A major challenge in designing a high speed NoC is the difficulty of distributing a high speed, low power clock across the chip. In this dissertation, we first propose several techniques to address the issue of distributing a high-speed, low power, low jitter clock across the IC. We primarily focus our attention on resonant standing wave oscillators (SWOs), which have recently emerged as a promising technique for high-speed, low power clock generation. In addition, we also present a dynamic programming based approach to synthesize a low jitter, low power buffered H-tree for clock distribution. In the second part of this dissertation, we use these efficient clock distribution schemes to present a novel fast NoC design that relies on source synchronous data transfer over a ring. In our source-synchronous design, the clock and data NoC are routed in parallel yielding a fast, robust design. Architectural simulations on synthetic and real traffic show that our source-synchronous NoC designs can provide significantly lower latency while achieving the same or better bandwidth compared to a state of the art mesh, while consuming lower area. The fact that the our ring-based NoC runs significantly faster than the mesh contributes to these improvements. Moreover, since our proposed NoC designs are fully synchronous, they are very amenable to testing as well. In the last part of this dissertation, we explore an alternate scheme of achieving high-speed on-chip data transfer using sinusoidal signals of different frequencies. The key advantage of our method is the ability to superimpose such sinusoids and thereby effectively send multiple logic values along the same wire in a clock cycle. Experimental results show that for the same throughput as that of a traditional scheme, we require significantly fewer wires.

Thesis (doctoral)--Université de Neuchatel, 1932. / Includes bibliographical references.

Diss.-Basel. / Issued also as: Basler betriebswirtschaftliche studien. Includes bibliographical references (p. x-xii).

Diss.-Basel. / Issued also as: Basler betriebswirtschaftliche studien. Includes bibliographical references (p. x-xii).

Important characteristic of any VLSI design circuit is its power reliability, high operating speed and low silicon area implementation. Dynamic CMOS designs provide high operating speeds compared to static CMOS designs combined with low silicon area requirement. The use of pipelines can also provide high circuit operating speeds. However, as the operating frequency increases, the number of pipeline stages should also increase and so the memory elements. These memory elements increases the area of implementation and restricts the maximum achievable frequency due to their delays. Memoryless pipelines based on dynamic design address these issues but, still requires high power consumption for the clock signal. In this thesis we present a sinusoidal three-phase clocking scheme that reduces the power required by the clock and offers high circuit operating frequencies. Thus the proposed technique provides advantages over preexisting techniques in terms of power requirement, area over head and operating speed.

The aim of this study was to determine the specific interactions among clock gene alleles in Drosophila melanogaster and their effect on the function of the circadian clock. The second part of this study deals with the expression pattern (both temporal and spatial) of two core clock factors known from Drosophila, period and timeless, in the central nervous system of the red flour beetle, Tribolium castaneum.

As processor clock frequencies continue to improve at a rate that exceeds the rate of improvement in the performance of semiconductor memories, so the effect of memory latency on processor efficiency increases. Unless steps are taken to mitigate the effect of memory latency, the increased processor frequency is of little benefit. This work demonstrates how multithreading can reduce the effect of memory latency on processor performance and how just a few threads are required to achieve close to optimal performance. A lightweight multithreaded architecture is discussed and simulated to show how threads derived from an application's instruction-level parallelism may be used to tolerate memory latency.