The soybean cyst nematode (SCN), Heterodera glycines, a plant parasitic pest, causes severe yield losses of soybean (Glycine max). Although a number of studies have identified various genes that function in defense, including a role for the vesicular transport machinery acting against H. glycines in infected roots, a regulatory mechanism occurring behind the transcriptional engagement of the vesicular transport system and delivery of the transported cargo proteins is not fully understood. The main goal of the current study is to determine the functional effect of genetically engineering the circadian clock gene, CIRCADIAN CLOCK ASSOCIATED 1 (CCA1) in G. max to examine a role on H. glycines parasitism. The outcome of the study has determined the functional effect of main clock component CCA1-1 along with other oscillator genes such as TIMING OF CAB 1 (TOC1-1), GIGANTEA (GI-1) and CONSTANS (CO-4) to enhance resistance against H. glycines parasitism. Further, the reduced level of the expression of Gm-CCA1-1 in infected roots, in comparison to uninfected roots, has demonstrated that clock components might have arrested and altered its expression during the nematode infection process. The study has also investigated the role of XYLOGLUCAN ENDO-TRANSGLYCOSYLASE /HYDROLASE (XTH), Gm-XTH43, during the resistance process soybean has to H. glycines. The results have demonstrated higher xyloglucan (XyG) amounts to be synthesized in the Gm-XTH43 overexpressing (OE) lines. In contrast, there is less XyG in the Gm-XTH43 RNA interference (RNAi) lines that have a negatively regulated XTH gene. These observations have led to elucidating the role in the potential cell wall rearrangement and the underlying metabolic processes required for the generation of the proper XyG architecture required for defense occurring outside of the plant cell. Furthermore, the observed result of lower level of weight average molecular weight (WAMW) of XyG in Gm-XTH43-OE and higher MW of XyG in Gm-XTH43-RNAi than respective control roots have demonstrated a key role in, presumably, changing the cell wall by the remodeling of the XyG chain as it relates to the cell wall architecture.

The clock is the important synchronizing element in all synchronous digital systems. The difference in the clock arrival time between sink points is called the clock skew. This uncertainty in arrival times will limit operating frequency and might cause functional errors. Various clock routing techniques can be broadly categorized into 'balanced tree' and 'fixed mesh' methods. The skew and delay using the balanced tree method is higher compared to the fixed mesh method. Although fixed mesh inherently uses more wire length, the redundancy created by loops in a mesh structure reduces undesired delay variations. The fixed mesh method uses a single mesh over the entire chip but it is hard to introduce clock gating in a single clock mesh. This thesis deals with the introduction of 'reconfigurability' by using control structures like transmission gates between sub-clock meshes, thus enabling clock gating in clock mesh. By using the optimum value of size for PMOS and NMOS of transmission gate (SZF) and optimum number of transmission gates between sub-clock meshes (NTG) for 4x4 reconfigurable mesh, the average of the maximum skew for all benchmarks is reduced by 18.12 percent compared to clock mesh structure when no transmission gates are used between the sub-clock meshes (reconfigurable mesh with NTG =0). Further, the research deals with a ‘modified zero skew method' to connect synchronous flip-flops or sink points in the circuit to the clock grids of clock mesh. The wire length reduction algorithms can be applied to reduce the wire length used for a local clock distribution network. The modified version of ‘zero skew method’ of local clock routing which is based on Elmore delay balancing aims at minimizing wire length for the given bounded skew of CDN using clock mesh and H-tree. The results of ‘modified zero skew method' (HC_MZSK) show average local wire length reduction of 17.75 percent for all ISPD benchmarks compared to direct connection method. The maximum skew is small for HC_MZSK in most of the test cases compared to other methods of connections like direct connections and modified AHHK. Thus, HC_MZSK for local routing reduces the wire length and maximum skew.

by Fok Oi-Ling Catherine, Cheung Tung-Lan Tony. / Thesis (M.B.A.)--Chinese University of Hong Kong, 1987. / Bibliography: leaves 99-100.

This thesis focuses on the circadian clock genes and their involvement in the photoperiodic time measurement in the linden bug, Pyrrhocoris apterus. Application of the molecular biology methods enabled us to propose the architecture of circadian clockwork. We also investigated the role of several previously undescribed players in the circadian clock. Furthermore, by using molecular biology methods we focused on the involvement of core circadian clock genes in the photoperiodism.

With the increasing system clock, a clock circuit will cause an amount of electromagnetic interference. To reduce EMI of the products, various EMI strategies have been developed. In the thesis, we study the suppression of electromagnetic interference of a clock circuit by using the spread spectrum technique. The basic idea of the spread spectrum is to slightly modulate the frequency of the clock signal and the energy of the signal will be dispersed to a controllable range to reduce the peak energy of each harmonic wave in the spectrum, and the products can pass the electromagnetic compatibility test more easily. We obtain the attenuation factor of spread spectrum from the theoretical derivation, including modulation index and modulation profiles. From the numerical simulation, we verify that spread spectrum technique can suppress the peak energy. We propose the attenuation formulas which can control the attenuation of every frequency point. To verify our findings, we use a spread spectrum clock generator from market to perform measurement. The trapezoidal waveform can be used to represent a clock circuit. Its waveform includes rise time and duty cycle. We will discuss the influence of rise time and duty cycle on the spread spectrum technique. Shorter rise time will cause high order harmonics in the high speed clock circuit. We verify that spread spectrum technique can suppress high order harmonics from both the simulation and experiment. Because every harmonic can be suppressed, the spread spectrum technique has the good suppression effect for the whole system.

Malhas de relógio são arquiteturas de rede de relógio adequadas para distribuir confiavelmente o sinal de relógio na presença de variações de processo e ambientais. Tal propriedade se torna muito importante nas tecnologias submicrônicas onde variações têm um papel importante. A confiabilidade da malha de relógio é devido aos caminhos redundantes conectando o sinal de relógio até os receptores de forma que variações afetando um caminho possam ser compensadas pelos outros caminhos. A confiabilidade vem ao custo de mais consumo de potência e fiação. Desta forma fica claro o balanceamento necessário entre distribuir confiavelmente o sinal de relógio (mais redundância) e o consumo de potência e aumento de fiação. O clock skew é definido como a diferença entre os tempos de chegada do sinal de clock nos seus receptores. Quanto maior é o clock skew, mais lento o circuito precisa operar. Além de diminuir a velocidade do circuito, um valor alto de clock skew aumenta a probabilidade de o circuito não funcionar devido às variações. Neste trabalho, nos focamos no problema de clock skew. Inicialmente extraímos informações úteis de como o comprimento da fiação e a capacitância variam a medida que o tamanho da malha varia. São apresentadas fórmulas analíticas que encontram o tamanho ótimo para ambos objetivos e é apresentado um estudo de como o clock skew varia a medida que nos afastamos do tamanho ótimo da malha de relógio. Um método para a redução de clock skew através do deslocamento dos buffers também é apresentado. Tal melhoria no clock skew não afeta o consumo de potência já que o tamanho dos buffers e a malha não são alterados. / Clock meshes are a suitable clock network architecture for reliably distributing the clock signal under process and environmental variations. This property becomes very important in the deep sub-micron technology where variations play a main role. The clock mesh reliability is due to redundant paths connecting clock buffers to clock sinks, so that variations affecting one path can be compensated by other paths. This comes at cost of more power consumption and wiring resources. Therefore it is clear the tradeoff between reliably distributing the clock signal (more redundancy) and the power and resource consumption. The clock skew is defined as the difference in the arrival time of clock signal at clock sinks. The higher is the clock skew, the slower is the circuit. Besides slowing down the circuit operation, a high clock skew increases the probability of circuit malfunction due to variations. In this work we focus on the clock skew problem. We first extract some useful information on how the clock wirelength and capacitance change as the mesh size changes. We present analytical formulas to find the optimum mesh size for both goals and study how the clock skew varies as we move further away from the optimum mesh size. We also present a method for reducing the clock mesh skew by sliding buffers from the position where they are traditionally placed. This improvement comes at no increasing cost of power consumption since the buffer size and the mesh capacitance are not changed.

Malhas de relógio são arquiteturas de rede de relógio adequadas para distribuir confiavelmente o sinal de relógio na presença de variações de processo e ambientais. Tal propriedade se torna muito importante nas tecnologias submicrônicas onde variações têm um papel importante. A confiabilidade da malha de relógio é devido aos caminhos redundantes conectando o sinal de relógio até os receptores de forma que variações afetando um caminho possam ser compensadas pelos outros caminhos. A confiabilidade vem ao custo de mais consumo de potência e fiação. Desta forma fica claro o balanceamento necessário entre distribuir confiavelmente o sinal de relógio (mais redundância) e o consumo de potência e aumento de fiação. O clock skew é definido como a diferença entre os tempos de chegada do sinal de clock nos seus receptores. Quanto maior é o clock skew, mais lento o circuito precisa operar. Além de diminuir a velocidade do circuito, um valor alto de clock skew aumenta a probabilidade de o circuito não funcionar devido às variações. Neste trabalho, nos focamos no problema de clock skew. Inicialmente extraímos informações úteis de como o comprimento da fiação e a capacitância variam a medida que o tamanho da malha varia. São apresentadas fórmulas analíticas que encontram o tamanho ótimo para ambos objetivos e é apresentado um estudo de como o clock skew varia a medida que nos afastamos do tamanho ótimo da malha de relógio. Um método para a redução de clock skew através do deslocamento dos buffers também é apresentado. Tal melhoria no clock skew não afeta o consumo de potência já que o tamanho dos buffers e a malha não são alterados. / Clock meshes are a suitable clock network architecture for reliably distributing the clock signal under process and environmental variations. This property becomes very important in the deep sub-micron technology where variations play a main role. The clock mesh reliability is due to redundant paths connecting clock buffers to clock sinks, so that variations affecting one path can be compensated by other paths. This comes at cost of more power consumption and wiring resources. Therefore it is clear the tradeoff between reliably distributing the clock signal (more redundancy) and the power and resource consumption. The clock skew is defined as the difference in the arrival time of clock signal at clock sinks. The higher is the clock skew, the slower is the circuit. Besides slowing down the circuit operation, a high clock skew increases the probability of circuit malfunction due to variations. In this work we focus on the clock skew problem. We first extract some useful information on how the clock wirelength and capacitance change as the mesh size changes. We present analytical formulas to find the optimum mesh size for both goals and study how the clock skew varies as we move further away from the optimum mesh size. We also present a method for reducing the clock mesh skew by sliding buffers from the position where they are traditionally placed. This improvement comes at no increasing cost of power consumption since the buffer size and the mesh capacitance are not changed.

Malhas de relógio são arquiteturas de rede de relógio adequadas para distribuir confiavelmente o sinal de relógio na presença de variações de processo e ambientais. Tal propriedade se torna muito importante nas tecnologias submicrônicas onde variações têm um papel importante. A confiabilidade da malha de relógio é devido aos caminhos redundantes conectando o sinal de relógio até os receptores de forma que variações afetando um caminho possam ser compensadas pelos outros caminhos. A confiabilidade vem ao custo de mais consumo de potência e fiação. Desta forma fica claro o balanceamento necessário entre distribuir confiavelmente o sinal de relógio (mais redundância) e o consumo de potência e aumento de fiação. O clock skew é definido como a diferença entre os tempos de chegada do sinal de clock nos seus receptores. Quanto maior é o clock skew, mais lento o circuito precisa operar. Além de diminuir a velocidade do circuito, um valor alto de clock skew aumenta a probabilidade de o circuito não funcionar devido às variações. Neste trabalho, nos focamos no problema de clock skew. Inicialmente extraímos informações úteis de como o comprimento da fiação e a capacitância variam a medida que o tamanho da malha varia. São apresentadas fórmulas analíticas que encontram o tamanho ótimo para ambos objetivos e é apresentado um estudo de como o clock skew varia a medida que nos afastamos do tamanho ótimo da malha de relógio. Um método para a redução de clock skew através do deslocamento dos buffers também é apresentado. Tal melhoria no clock skew não afeta o consumo de potência já que o tamanho dos buffers e a malha não são alterados. / Clock meshes are a suitable clock network architecture for reliably distributing the clock signal under process and environmental variations. This property becomes very important in the deep sub-micron technology where variations play a main role. The clock mesh reliability is due to redundant paths connecting clock buffers to clock sinks, so that variations affecting one path can be compensated by other paths. This comes at cost of more power consumption and wiring resources. Therefore it is clear the tradeoff between reliably distributing the clock signal (more redundancy) and the power and resource consumption. The clock skew is defined as the difference in the arrival time of clock signal at clock sinks. The higher is the clock skew, the slower is the circuit. Besides slowing down the circuit operation, a high clock skew increases the probability of circuit malfunction due to variations. In this work we focus on the clock skew problem. We first extract some useful information on how the clock wirelength and capacitance change as the mesh size changes. We present analytical formulas to find the optimum mesh size for both goals and study how the clock skew varies as we move further away from the optimum mesh size. We also present a method for reducing the clock mesh skew by sliding buffers from the position where they are traditionally placed. This improvement comes at no increasing cost of power consumption since the buffer size and the mesh capacitance are not changed.

Les neurones à Kisspeptine (Kp) de l'AVPV sont essentiels pour la survenue du pic de LH. Celle-ci est conditionnée par les concentrations circulantes d'oestrogènes (E2) et le moment du jour. Nous avons étudié si les neurones à Kp de l'AVPV étaient le lieu d'intégration de deux messages chez des souris sauvages intactes : un message E2, et un message temporel. Nous voulions savoir si ces neurones hébergeaient une horloge secondaire impliquée dans la temporalité du pic de LH. Durant l'après-midi du proestrus, une baisse drastique de l'immunoréactivité (ir) de Kp apparaît 2h avant la survenue du pic de LH au moment où l'expression de l'ARNm Kiss1 est élevée. Au contraire durant le diestrus, Kpir,l'expression de l'ARNm Kiss1 et les concentrations circulantes de LH restent basses. Les neurones à Kp de l'AVPV expriment une protéine horloge PER1 avec un rythme journalier exhibant un retard de phase de 2.8 h en diestrus comparativement au proestrus. Des explants d'AVPV exprimant les Kp provenant de souris PER2::LUCIFERASE dévoilent des oscillations circadiennes soutenues avec une période de 23.2h, significativement plus courte que celle observée dans les NSC. L'incubation des explants d'AVPV en présence d'E2 (10nM) rallonge la période d'une heure. En conclusion, cette étude indique que les neurones à Kp de l'AVPV présentent un rythme journalier dépendant des E2, qui pourrait être piloté par la présence d'une horloge secondaire au sein de ces neurones. / The kisspeptin (Kp) neurons in the anteroventral periventricular nucleus (AVPV) are essential for the preovulatory LH surge, which is gated by circulating estradiol (E2) and the time of day. We investigated whether AVPV Kp neurons in intact female mice may be the site in which both E2 and daily signals are integrated and whether these neurons may host a circadian oscillator involved in the timed LH surge. In the afternoon of proestrous day, Kp immunoreactivity displayed a marked and transient decrease 2 hours before the LH surge. In contrast, Kp content was stable throughout the day of diestrus, when LH levels are constantly low. AVPV Kp neurons expressed the clock protein period1 (PER1) with a daily rhythm that is phase delayed compared with the PER1 rhythm measured in the main clock of the suprachiasmatic nuclei (SCN). PER1 rhythm in the AVPV, but not in the SCN,exhibited a significant phase delay of 2.8 hours in diestrus as compared with proestrus. Isolated Kp expressing AVPV explants from PER2::LUCIFERASE mice displayed sustained circadian oscillations of bioluminescence with a circadian period (23.2 h) significantly shorter than that of SCN explants(24.5 h). Furthermore, in AVPV explants incubated with E2 (10 nM to 1 μM), the circadian period was lengthened by 1 hour, whereas the SCN clock remained unaltered. In conclusion, these findings indicate that AVPV Kp neurons display an E2-dependent daily rhythm, which may possibly be driven by an intrinsic circadian clock acting in combination with the SCN timing signal.

Wireless Sensor Networks (WSNs) consist of a large number of resource constrained sensor nodes equipped with various sensing devices which can monitor events in the real world. There are various applications such as environmental monitoring, target tracking forest fire detection, etc., which require clock synchronization among the sensor nodes with certain accuracy. However, a major constraint in the design of clock synchronization protocols in WSNs is that sensor nodes of WSNs have limited energy and computing resources. Clock synchronization process in the WSNs is carried out at each sensor node either synchronously, i.e., periodically during the same real-time interval, which we call synchronization phase, or asynchronously, i.e., independently without worrying about what other nodes are doing for clock synchronization. A disadvantage of asynchronous clock synchronization protocols is that they require the sensor nodes to remain awake all the time. Therefore, they cannot be integrated with any sleep-wakeup scheduling scheme of sensor nodes, which is a major technique to reduce energy consumption in WSNs. On the other hand, synchronous clock synchronization protocols can be easily integrated with the synchronous sleep-wakeup scheduling scheme of sensor nodes, and at the same time, they can provide support to achieve sleep-wakeup scheduling of sensor nodes. Essentially, there are two ways to synchronize the clocks of a WSN, viz. internal clock synchronization and external clock synchronization. The existing approaches to internal clock synchronization in WSNs are mostly hop-by-hop in nature, which is difficult to maintain. There are also many application scenarios where external clock synchronization is the only option to synchronize the clocks of a WSN. Besides, it is also desired that the internal clock synchronization protocol used is fault-tolerant to message loss and node failures. Moreover, when the external source fails or reference node fails, the external clock synchronization protocol should revert back to internal clock synchronization protocol with/without using any reference node. Towards this goal, first we propose three fully distributed synchronous clock synchronization protocols, called Energy Efficient and Fault-tolerant Clock Synchronization (EFCS) protocol, Weighted Average Based Internal Clock Synchronization (WICS) protocol, and Weighted Average Based External Clock Synchronization (WECS) protocol, for WSNs making use of peer-to-peer approach. These three protocols are dynamically interchangeable depending upon the availability of external source or reference nodes. In order to ensure consistency of the synchronization error in the long run, the neighboring nodes need to be synchronized with each other at about the same real time, which requires that the synchronization phases of the neighboring nodes always overlap with each other. To realize this objective, we propose a novel technique of pullback, which ensures that the synchronization phases of the neighboring nodes always overlap. In order to further improve the synchronization accuracy of the EFCS, WICS, and WECS protocol, we have proposed a generic technique which can be applied to any of these protocols, and the improved protocols are referred as IEFCS, IWICS, and IWECS respectively. We then give an argument to show that the synchronization error in the improved protocols is much less than that in the original protocols. We have analyzed these protocols for bounds on synchronization error, and shown that the synchronization error is always upper bounded. We have evaluated the performance of these protocols through simulation and experimental studies, and shown that the synchronization accuracy achieved by these protocols is of the order of a few clock ticks even in very large networks. The proposed protocols make use of estimated drift rate to provide logical time from the physical clock value at any instant and at the same time ensure the monotonicity of logical time even though physical clock is updated at the end of each synchronization phase. We have also proposed an energy aware routing protocol with sleep scheduling, which can be integrated with the proposed clock synchronization protocols to reduce energy consumption in WSNs further.