In this modern landscape where families are spending increasing time living separately, due to parental separation, work travel, and illness, current communication technologies do not fully support the needs of intimate family communication in families with young children, aged two to nine. Prolonged separation, without intimate communication, can damage parent and child relationships, impacting on intimacy, bonding, and a child’s mental health and wellbeing. Care and play activities are the main methods used to build bonds between parent and child. These are hard to replicate with ubiquitous communication technologies when families are separated. Ubiquitous technology, such as the telephone, is easy to use but does not offer engaging ways for a child to interact. Skype (video call), has a higher potential for engagement due to its multimodal nature (audio and visual), therefore is more emotionally expressive. However, to ‘Skype’ someone, a child requires adult support, as the technology is more complex to use than that of a telephone. Thus, neither the telephone or Skype fully meet family needs for communication. Parental-child separation was looked at within parental separation, work travel and illness, to explain how intimacy can be achieved through technology mediated communication systems. Following a Participatory Action Research methodology, utilising methods such as co-design, co-creation, and participatory design, the research discusses five small-scale studies as well as the Trace project, which was the main study of this research. This research addresses communication issues between families through textile-based communication systems which enable intimacy and bonding. It highlights the importance of intimate communications and offers a list of preferred modes of communication for scattered families (multimodal disparate objects that allow for synchronous or asynchronous communications with either the same modes or different modes of input and output). It also outlines key methods for designing new technologies suitable for use in family research (inclusive methods such as co-design, co-creation and participatory design). A better understanding of the participant families’ emotional needs was achieved, by allowing them to become active participants at every stage of the design process (planning, acting, observing, and reflecting), thus producing considerate technologies for remote family communications.

Denna studie undersöker interaktivt berättande och lärande på webben som medium. Syftet är att studien ska resultera i kunskap om hur man kan gå tillväga för att skapa en interaktiv berättelse som kommunicerar och lär ut till målgruppen. Det grundläggande forskningsproblemet som försökte lösas var att besvara hur man kan skapa en interaktiv berättelse som genom sina komponenter assisterar i att lära ut till målgruppen. Studien har haft kvalitativa fokusgruppsintervjuer som metod. I anslutning till fokusgruppsintervjun hölls en workshop med inslag av co-design. Detta för att undersöka målgruppens syn på interaktivt berättande och lärande på webben. Målgruppen har definierats som digital natives i åldern 18–25 år. Valet av målgrupp motiveras med att de spenderar en övervägande stor tid på internet. Det teoretiska ramverket för studien är teorier som berör interaktivt berättande, co-design samt lärande. Studien utgick från detta ramverk i analysen av insamlade data från fokusgruppen. Därefter skapades en prototyp baserat på resultatet från studien och efter det utvärderades prototypen tillsammans med två deltagare från tidigare fokusgrupp. Genom analysen framkom flera insikter utifrån målgruppens syn på interaktivt berättande. Några av dessa insikter var att de interaktiva aspekterna av webbsidan ska harmonisera med innehållet. Webbsidan ska vara dynamisk och multisensorisk, bild och ljud ska assistera övrigt innehåll. En webbsida med en hög grad interaktivitet är möjligen fördelaktig för att skapa engagemang och få uppmärksamhet men kan samtidigt vara förvirrande i brist på struktur. Detta sammanfattades och konkretiserades i en första iteration av prototypen. Uppsatsen presenterar en lösning på problemet gällande hur en interaktiv berättelse kan användas för att lära ut på webben. Prototypen som skapades är en möjlig lösning på denna problematik. Implikationer till fortsatt forskning är att undersöka den äldre målgruppen digital immigrants. / This study investigates interactive storytelling and learning on the web as a medium. The aim for this study is to result in knowledge of how to create interactive storytelling that through its components communicate with and educate the target group. The core research problem that we attempted to solve was; how to create an interactive story that educates the target audience. This study has had a qualitative research method, specifically focus groups. Within the focus group interview, a workshop with elements of co-design was included. The reason for this was to investigate the audience's view of interactive storytelling and learning on the web. The target group has been defined as digital natives within the age span of 18 – 25 years. The reason for choosing this target group is motivated by them spending a predominantly large amount of time on the Internet. The theoretical framework for this study is theories in relation to interactive storytelling, co-design and learning. This theoretical framework was used in the analysis of the data collected during the focus group interview. A prototype was created based on the results of the study. The prototype was then evaluated together with two participants from the previous focus group. The analysis revealed several insights based on the audience's view of interactive storytelling. In the following text, some of the insights are described. The interactive aspects of the webpage should harmonize with the content. The webpage should be dynamic and multisensory, images and sound should assist other content. A webpage with a large amount of interactivity might be advantageous for gaining the users interest and attention but can also be confusing if lacking in structure. This information was summarized and applied in the creation of the first iteration of the prototype This essay presents a solution to the question of how an interactive story can be applied and used for education on the web. The prototype created is a possible solution to this problem. Implications for further research could be to investigate an older target group, such as digital immigrants.

This thesis presents design automation methodologies for extensible processor platforms in application specific domains. The work presents first a single processor approach for customization; a methodology that can rapidly create different processor configurations by the removal of unused instructions sets from the architecture. A profile directed approach is used to identify frequently used instructions and to eliminate unused opcodes from the available instruction pool. A coprocessor approach is next explored to create an SoC (System-on-Chip) to speedup the application while reducing energy consumption. Loops in applications are identified and accelerated by tightly coupling a coprocessor to an ASIP (Application Specific Instruction-set Processor). Latency hiding is used to exploit the parallelism provided by this architecture. A case study has been performed on a JPEG encoding algorithm; comparing two different coprocessor approaches: a high-level synthesis approach and our custom coprocessor approach. The thesis concludes by introducing a heterogenous multi-processor system using ASIPs as processing entities in a pipeline configuration. The problem of mapping each algorithmic stage in the system to an ASIP configuration is formulated. We proposed an estimation technique to calculate runtimes of the configured multiprocessor system without running cycle-accurate simulations, which could take a significant amount of time. We present two heuristics to efficiently search the design space of a pipeline-based multi ASIP system and compare the results against an exhaustive approach. In our first approach, we show that, on average, processor size can be reduced by 30%, energy consumption by 24%, while performance is improved by 24%. In the coprocessor approach, compared with the use of a main processor alone, a loop performance improvement of 2.57x is achieved using the custom coprocessor approach, as against 1.58x for the high level synthesis method, and 1.33x for the customized instruction approach. Energy savings are 57%, 28% and 19%, respectively. Our multiprocessor design provides a performance improvement of at least 4.03x for JPEG and 3.31x for MP3, for a single processor design system. The minimum cost obtained using our heuristic was within 0.43% and 0.29% of the optimum values for the JPEG and MP3 benchmarks respectively.

Cette thèse a fait partie du projet MIMOC (Méthodes d'Intégration et de Miniaturisation d'Objets Communicants) qui a été mené à terme en partenariat avec le laboratoire IM2NP de Marseille, la société InsightSiP à Sophia Antipolis et Orange Labs La Turbie. Le projet cible les systèmes de transmission par impulsions occupant une très large bande de fréquences (signaux Ultra Large Bande : ULB). Au sein de ce projet, les travaux de cette thèse ont été concentrés sur le développement, la miniaturisation et l'intégration des antennes dans des systèmes de communications ULB conformes aux normes Américaines (FCC :3.1-10.6 GHz) et Européennes (ECC : 6-8.5 GHz). Le développement d'une antenne consiste à en maîtriser les différents paramètres en analysant leurs influences sur l'adaptation et le rayonnement de celle-ci. Une étude préliminaire a permis de créer une base de données qui a été utilisée par la suite dans les différentes phases du projet afin de réadapter l'élément en fonction de l'évolution de son environnement. Un élément rayonnant imprimé constitué de plusieurs étages rectangulaires, alimenté par la ligne ground coplanaire (GCPW), adapté dans la bande de fréquence FCC, a servi de base d'étude. Cette antenne a été étudiée dans deux configurations correspondant à deux types d'applications : un format carte de crédit et un format clé USB, principalement distinguées par leur encombrement lié à la largeur des plans de masse. L'étude a débuté avec une structure à plan de masse large et a été suivie, dans une deuxième phase, par des travaux de miniaturisation. La miniaturisation consiste à réduire la largeur des plans de masse en modifiant la géométrie de la structure afin de conserver ses performances radioélectriques. Plusieurs techniques ont été étudiées, notamment la réduction de l'encombrement par repliements 2D et 3D. La technique la plus efficace fut celle basée sur l'insertion de découpes au niveau des plans de masse latéraux ainsi qu'au niveau des plans de masse inférieurs. Une bonne maîtrise des dimensions de ces encoches a permis d'obtenir une structure réduite d'un facteur 5 avec une bonne adaptation sur toute la bande de fréquences. Ces structures ont ensuite été réalisées et les prototypes ont été caractérisés. La caractérisation s'est déroulée lors de plusieurs campagnes de mesures au LEAT et à Orange Labs à La Turbie. Un banc de test a été entièrement développé et des mesures dans les domaines temporel et fréquentiel ont permis d'extraire les performances des antennes : gain, diagramme de rayonnement, réponse impulsionnelle, facteur de fidélité, etc. La capacité d'une transmission à travers ces prototypes a été vérifiée en environnement réel. Des débits allant jusqu'à 500Mbits/s ont été atteint. La troisième phase des travaux a consisté à modéliser une puce génératrice d'impulsions ULB et l'intégrer en l'assemblant avec l'antenne dans un système. Cette étude a été réalisée dans la bande ULB européenne ECC. Un nouvel élément imprimé et miniaturisé adapté dans cette bande de fréquences a du être conçu. La puce a totalement été modélisé et paramétrée de façon à ce qu'elle soit prise en compte lors de la conception du système. Le projet MIMOC a été achevé avec succès. Le bon partenariat avec tous les membres s'est avéré très constructif et a permis de réaliser le codesign de la partie "antenne" et de la partie "microélectronique". Suite à ces travaux, un autre projet qui consiste à développer des systèmes communicants en contact avec le corps humain (RUBY) vient de démarrer.

Advances in microelectronics technology have enabled us to integrate a complex electronic system (such as a radio) on a single chip or in a single package module, known as system-on-chip (SoC) and system-on-package (SoP) paradigms. This brings not only new opportunities for system integration, but also challenges in design and implementation. One of these challenges is how to achieve an optimum total solution of system integration via chip and package co-design, because there is no tool or design methodology available for such kind of optimization. This thesis focuses on innovative multi-band multi-standard radio front-end design and explores a new design methodology. The motivation of developing this design methodology is to achieve an optimum total solution for radio system implementation via chip and package co-design and co-optimization. The methodology starts from RF packaging and components modeling. Necessary models for both on-chip and off-chip passives are developed. Parasitic effects of packages for radio chips are modeled for particular frequencies. Compared with high-speed digital packaging, RF packaging normally deals with narrow band signals. It is possible to absorb some unwanted parasitics by designing proper port matching networks. In addition, cost-performance trade-offs are performed. In this context, we first developed process and technology based cost models, which include parameters like chip real estate, raw materials, package, test and rework. Impact of process variation on final yield has also been considered in the models by using a statistical analysis approach. Performance of different design options is measured by a special FoM (figure-of-merit). Each type of analog/RF circuit (such as LNA, PA and ADC) has its own dedicated FoM. Through a series of cost-performance trade-offs for different on-chip versus off-chip passives and partitions, an optimum total solution is obtained. Finally, this methodology was demonstrated via a number of design examples for multi-band multi-standard radio front-end. The author has explored the optimum solutions for different circuit architectures and process technologies encompassing parallel, concurrent and digitally programmable multi-band radio frond-end blocks. It is interesting to find that, for complex RF circuits like a multi-band multi-standard radio, moving some passives off-chip will have significant cost-savings. In addition to the above contributions, the author has also developed an MCM-D technology on LCP and glass substrates, based on metal deposition and BCB spin-coating at KTH clean room. The author has also performed some preliminary studies on UWB radio for RFID applications. / QC 20101005

QC 20101018

Field Programmable Gate Arrays (FPGAs) are a reconfigurable hardware platform which enable the acceleration of software code through the use of custom-hardware circuits. Complex systems combining processors with programmable logic require partitioning to decide which code segments to accelerate. This thesis provides tools to help determine which software code sections would most benefit from hardware acceleration. A low-overhead profiling architecture, called LEAP, is proposed to attain real-time profiles of an FPGA-based processor. LEAP is designed to be extensible for a variety of profiling tasks, three of which are investigated and implemented to identify candidate software for acceleration. 1) Cycle profiling determines the most time-consuming functions to maximize speedup. 2) Cache stall profiling detects memory-intensive code; large memory overheads reduce the benefits of acceleration. 3) Energy consumption profiling detects energy-inefficient code through the use of an instruction-level power database to minimize the system's energy consumption.

A hardware implementation can bring orders of magnitude improvements in performance and energy consumption over a software implementation. Hardware design, however, can be extremely difficult. High-level synthesis, the process of compiling software to hardware, promises to make hardware design easier. However, compiling an entire software program to hardware can be inefficient. This thesis proposes hardware/software co-design, where computationally intensive functions are accelerated by hardware, while remaining program segments execute in software. The work in this thesis builds a framework where user-designated software functions are automatically compiled to hardware accelerators, which can execute serially or in parallel to work in tandem with a processor. To support multiple parallel accelerators, new multi-ported cache designs are presented. These caches provide low-latency high-bandwidth data to further improve the performance of accelerators. An extensive range of cache architectures are explored, and results show that certain cache architectures significantly outperform others in a processor/accelerator system.

Field Programmable Gate Arrays (FPGAs) are a reconfigurable hardware platform which enable the acceleration of software code through the use of custom-hardware circuits. Complex systems combining processors with programmable logic require partitioning to decide which code segments to accelerate. This thesis provides tools to help determine which software code sections would most benefit from hardware acceleration. A low-overhead profiling architecture, called LEAP, is proposed to attain real-time profiles of an FPGA-based processor. LEAP is designed to be extensible for a variety of profiling tasks, three of which are investigated and implemented to identify candidate software for acceleration. 1) Cycle profiling determines the most time-consuming functions to maximize speedup. 2) Cache stall profiling detects memory-intensive code; large memory overheads reduce the benefits of acceleration. 3) Energy consumption profiling detects energy-inefficient code through the use of an instruction-level power database to minimize the system's energy consumption.

A hardware implementation can bring orders of magnitude improvements in performance and energy consumption over a software implementation. Hardware design, however, can be extremely difficult. High-level synthesis, the process of compiling software to hardware, promises to make hardware design easier. However, compiling an entire software program to hardware can be inefficient. This thesis proposes hardware/software co-design, where computationally intensive functions are accelerated by hardware, while remaining program segments execute in software. The work in this thesis builds a framework where user-designated software functions are automatically compiled to hardware accelerators, which can execute serially or in parallel to work in tandem with a processor. To support multiple parallel accelerators, new multi-ported cache designs are presented. These caches provide low-latency high-bandwidth data to further improve the performance of accelerators. An extensive range of cache architectures are explored, and results show that certain cache architectures significantly outperform others in a processor/accelerator system.