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Multiple Instruction, Multiple Data (MIMD) networks can produce scalable processing power for a wide variety of image computing applications. For certain tasks however, data-distribution bottlenecks reduce the maximum achievable performance gain. Digital Signal Processing (DSP) technology is capable of high performance from a single processor, thus avoiding some of the data communication problems associated with multi-processor systems. Nevertheless, many practical applications require the incorporation of processing primitives provided by single computational elements, such as DSP, within a more general computational domain. The Fast Fourier Transform (FT) is typical of a class of algorithm frequently used in image processing that can be computed by a single DSP processor in the same time interval as a system containing many MIMD processors. The work investigates the design, construction and properties of a hierarchical computing system, capable of implementing complete FT transforms on two dimensional data structures. The basic hardware comprises a proprietary DSP processor, a controlling transputer and multiple, switched, banks of fast static random access memory (SRAM). The design strategy successfully allows the arithmetic operations of the DSP processor to be concurrent with the data exchange and input/output activities of the controlling transputer. The complexity of the resulting system prompted an investigation into structured design techniques. As the normal specification language Z has been shown to be a useful tool for software system design and documentation, its value in the design of a hardware system is explored. The way in which Z is utilised differs from existing applications to software system development, especially in the method of refinement towards a combined system of hardware, programmable logic and control software. After extensive design, construction and testing phases, initial validation shows that while the accelerator is a very powerful resource, capable of a complete 1024 point, one dimensional FFT in 560s, an efficiency of 45&'37 is difficult to exceed when repeated transforms are calculated.

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A distributed real-time computer system consists of several processing nodes interconnected by communication channels. In a safety critical application, the real-time system should maintain timely and dependable services despite component failures or transient overloads due to changes in application environment. When a component fails or an overload occurs, the hard real-time tasks may miss their timing constraints, and it is desired that the system to degrade in a graceful, predictable manner. The approach adopted to the problem in this thesis is by integrating the resource scheduling with fault tolerance mechanism. This thesis provides a basis for the modelling and design of an adaptive fault tolerant distributed real-time computer system. The main issue is to determine a priori the worst case timing response of the given hard realtime tasks. In this thesis the worst case timing response of the given hard real-time task of the distributed system using the Controller Area Network (CAN) communication protocol is evaluated as to whether they can satisfy their timing deadlines. In a hard real-time system, the task scheduling is the most critical problem since the scheduling strategy ensures that tasks meet their deadlines. In this thesis several fixed priority scheduling schemes are evaluated to select the most efficient scheduler in terms of the bus utilisation and access time. Static scheduling is used as it can be considered to be most appropriate for safety critical applications since the schedulability can easily be verified. Furthermore for a typical industrial application, the hard real-time system has to be adaptable to accommodate changes in the system or application requirements. This .goal of flexibility can be achieved by integrating the static scheduler using an imprecise computation technique with the fault tolerant mechanism which uses active redundant components.

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No description available.