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The Global ETD Search service is a free service for researchers
to find electronic theses and dissertations. This service is
provided by the
Networked Digital Library of Theses and Dissertations.
Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
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Showing 161 to 170 of 440 (0.042 seconds)Spelling suggestions: "subject:"computer hardware"" "subject:"coomputer hardware""
| 161 |
Real time simulation of complex power systems using parallel processorsBerry, T. January 1989 (has links)
No description available.
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| 162 |
Dynamic branch prediction in high performance superscalar processorsEgan, Colin January 2000 (has links)
No description available.
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| 163 |
Design of microprocessor-based hardware for number theoretic transform implementationShamim, Anwar Ahmed January 1983 (has links)
Number Theoretic Transforms (NTTs) are defined in a finite ring of integers Z (_M), where M is the modulus. All the arithmetic operations are carried out modulo M. NTTs are similar in structure to DFTs, hence fast FFT type algorithms may be used to compute NTTs efficiently. A major advantage of the NTT is that it can be used to compute error free convolutions, unlike the FFT it is not subject to round off and truncation errors. In 1976 Winograd proposed a set of short length DFT algorithms using a fewer number of multiplications and approximately the same number of additions as the Cooley-Tukey FFT algorithm. This saving is accomplished at the expense of increased algorithm complexity. These short length DFT algorithms may be combined to perform longer transforms. The Winograd Fourier Transform Algorithm (WFTA) was implemented on a TMS9900 microprocessor to compute NTTs. Since multiplication conducted modulo M is very time consuming a special purpose external hardware modular multiplier was designed, constructed and interfaced with the TMS9900 microprocessor. This external hardware modular multiplier allowed an improvement in the transform execution time. Computation time may further be reduced by employing several microprocessors. Taking advantage of the inherent parallelism of the WFTA, a dedicated parallel microprocessor system was designed and constructed to implement a 15-point WFTA in parallel. Benchmark programs were written to choose a suitable microprocessor for the parallel microprocessor system. A master or a host microprocessor is used to control the parallel microprocessor system and provides an interface to the outside world. An analogue to digital (A/D) and a digital to analogue (D/A) converter allows real time digital signal processing.
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| 164 |
A high speed digital dynamic simulatorMcCullough, H. January 1984 (has links)
No description available.
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| 165 |
Register transfer level simulation using pascal-plus in the design of microprogrammable microcomputersMuhammad, G. January 1982 (has links)
No description available.
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| 166 |
Dense instruction set computer architectureSchoepke, Olaf S. January 1992 (has links)
No description available.
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| 167 |
Network flow method for power system analysisDandachi, Najib H. January 1989 (has links)
No description available.
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| 168 |
On the design of a processor node for the direct manipulation of asynchronous transfer mode cellsJones, Gary B. January 2001 (has links)
No description available.
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| 169 |
A Pascal-based hardware and software description systemClark, Andrew N. January 1982 (has links)
No description available.
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| 170 |
Digital modems for mobile systemsCheung, Si-Wai January 1986 (has links)
No description available.
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