Currently, many machine vision, signal and image processing problems are solved on personal computers due to the low cost involved in these computers and the many excellent software tools that exist, such as MATLAB. However, computationally expensive tasks require the use of multi-processor computers that are expensive and difficult to use efficiently due to communications between the processors. In these cases, FPGAs (Field Programmable Gate Arrays) are the best choice but they are not as widely used because of lack of experience in using these devices, difficulties with algorithmic translation and immaturity of the design and implementation tools for FPGAs. Programming languages are always evolving and the programming languages for microprocessors have evolved significantly, from functional and procedural languages to object-oriented languages. Nowadays, a new paradigm called aspect-oriented software development (AOSD) is becoming more widespread. However, hardware programming languages have not evolved to the same extent as the software programming languages for microprocessors. They are still dominated by the technologies developed in 1980s, which have significant deficiencies described in this thesis. Recent advances in HDLs (Hardware Description Languages) have taken a conservative approach based on well-proven software techniques.

Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1991. / Vita. Abstract. Includes bibliographical references (leaves 91-94). Also available via the Internet.

Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1991. / Vita. Abstract. Includes bibliographical references (leaf 107). Also available via the Internet.

Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1992. / Vita. Abstract. Includes bibliographical references (leaves 56-57). Also available via the Internet.

Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1993. / Vita. Abstract. Includes bibliographical references (leaves 147-149). Also available via the Internet.

Thesis (M.A.)--Wright State University, 1990. / Cover title. "June 1990." Includes bibliographical references.

This research generates a large collection of optimized trajectories for multi-agent quadrotors. The hybridized algorithm extracts trajectories with various trade-off for all agents without discrimination. This allows the resources of all agents to contribute towards the completion of a task. Two variations of multi-agent quadrotor missions are applied within this work. The first is spatially spread flight mission, MA-SPREAD whereas the second is formation flight, MA-FORMATION. The trajectories are designed within three environments: i) Highly Cluttered Indoor, ii) Cityscape and iii) Mountainous terrain. The initial path nodes are generated through a sampling based planner. Here, Rapidly Exploring Random Trees is expanded into Multi-Agent Rapidly Exploring Random Forest. These paths are used to form the initial population for Genetic Algorithm. Next, we apply Many-Objectives Optimization towards the optimization of all agents and its objectives. This study strikes a balance between diverse and well minimized solutions through dimensionality reduction. Result shows that the algorithm can successfully find a diverse set of well minimized solutions within each environment. The end user will be supplied with high resolution visual imagery of each test environment and well-organized data that defines the trade-offs of each trajectory. These easy to understand information will assist the end user in making a final choice regarding the best multi-agent quadrotor trajectories for their mission.

In the growing field of digital system design, there is a great need for design tools that will assist the engineer in developing large scale systems. AHPL, A Hardware Programming Language, is a hardware description language which allows a digital system to be described, evaluated, and analyzed. But like many design tools, AHPL cannot satisfy the multitude of design tool applications. In order to enhance the power of AHPL as a design tool, an EDIF translator is developed. The EDIF translator generates an EDIF netlist of an AHPL design, thus making it possible to port AHPL designs to other design tools.

In this research, an AHPL (A Hardware Programming Language) based automation system is used to design and verify the Intel-8080 microprocessor from the RTL (Register Transfer Level) hardware description through the network list of transistors. The HPSIM is used as a RTL simulator which interprets the AHPL description and executes the connections, branches, and register transfer, and prints line or register values for each circuit clock period. After the AHPL description has been translated to switch-level link list, ESIM is applied for more detailed simulation to ensure the digital behavior in this microprocessor design is correct. The ESIM is an event-driven switch-level simulator which accepts commands from the user, and executes each command before reading the next one. After performing these different levels of simulations, a comparison is discussed at the end.

The use of Computer Hardware Description Languages plays an important role in the design automation process of digital systems. These languages help hardware engineers to provide a precise description of the internal structure of a system, and one of the most significant uses of these languages is as a means of input to a system simulator. AHPL is a hardware description language that describes a digital system as a set of modules and units. This language is supported by a function-level simulator (HPSIM2), but the simulator only provides support to the module descriptions of a system. This paper presents an improved version of the simulator that supports the use of unit descriptions called Combinational Logic Units or CLUNITs. The syntax and structure of a CLUNIT is analyzed, the operation and data structure of the simulator is given; and several examples are given to support these discussions.