Spelling suggestions: "subject:"computer hardware"" "subject:"coomputer hardware""
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Reanimating cultural heritage through digital technologiesZhang, Wei January 2011 (has links)
Digital technologies are becoming extremely important for web-based cultural heritage applications. This thesis presents novel digital technology solutions to 'access and interact' with digital heritage objects and collections. These innovative solutions utilize service orientation (web services), workflows, and social networking and Web 2.0 mashup technologies to innovate the creation, interpretation and use of collections dispersed in a global museumscape, where community participation is achieved through social networking. These solutions are embedded in a novel concept called Digital Library Services for Playing with Shared Heritage (DISPLAYS). DISPLAYS is concerned with creating tools and services to implement a digital library system, which allows the heritage community and museum professionals alike to create, interpret and use digital heritage content in visualization and interaction environments using web technologies based on social networking. In particular, this thesis presents a specific implementation of DISPLAYS called the Reanimating Cultural Heritage system, which is modelled on the five main functionalities or services defined in the DISPLAYS architecture, content creation, archival, exposition, presentation and interaction, for handling digital heritage objects. The main focus of this thesis is the design of the Reanimating Cultural Heritage system's social networking functionality that provides an innovative solution for integrating community access and interaction with the Sierra Leone digital heritage repository composed of collections from the British Museum, Glasgow Museums and Brighton Museum and Art Gallery. The novel use of Web 2.0 mashups in this digital heritage repository also allows the seamless integration of these museum collections to be merged with user or community generated content, while preserving the quality of museum collections data. Finally, this thesis tests and evaluates the usability of the Reanimating Cultural Heritage social networking system, in particular the suitability of the digital technology solution deployed. Testing is performed with a user group composed of several users, and the results obtained are presented.
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Suitability of the SRC-6E reconfigurable computing system for generating false radar image /Macklin, Kendrick R. January 2004 (has links) (PDF)
Thesis (M.S. in Computer Science)--Naval Postgraduate School, June 2004. / Thesis advisor(s): Neil Rowe. Includes bibliographical references (p. 129-130). Also available online.
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Benchmarking and analysis of the SRC-6E reconfigurable computing system /Macklin, Kendrick R. January 2003 (has links) (PDF)
Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, December 2003. / Thesis advisor(s): Douglas Fouts, Ted Lewis. Includes bibliographical references (p. 125). Also available online.
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Kompiuterio aparatinės įrangos mokomoji programa / Training programme of computer hardwareGricienė, Vilma 09 January 2006 (has links)
Recently the state budgets more and more resources for the computerization of schools. The computer capacities increase. However we confront a new problem- creating the software. There is a shortage of Lithuanian training programmes at schools. Purpose of the current work is to create a training programme of computer hardware that is easily managed and not demanding special skills, intended for the junior schoolchildren and computer users at the initial level. Analysis of the available programmes evidences the absence of such Lithuanian programme. The project has been worked out for the programme. Consumer demands, requirements, experience and skills have been investigated and estimated, functional and non functional requirements of the programme have been examined and the specification has been arranged. Programme architecture has been described in the architectural specification. Visual Basic Programming Language has been selected for the programme implementation. On the ground of testing document a testing of the programme has been carried out and mistakes revealed during the testing were eliminated. Consumer’s documentation has been prepared. The carried out analysis of the programme quality showed that the programme conforms the requirements raised for the training computer programmes and satisfies the demands of IT teachers, schoolchildren and users at the initial level.
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Modeling and Design of Spin Torque Transfer Magnetoresistive Random Access MemoryHuda, Safeen 15 November 2013 (has links)
This thesis presents the modeling and design of memory cells for Spin Torque Transfer Magnetoresistive Random Access Memory (STT-MRAM). The theory of operation of STT-MRAM cells is explored, and a model to predict the transient behaviour of STT-MRAM cells is presented. A novel three-terminal Magnetic Tunneling Junction (MTJ) and its associated cell structure is also presented. The proposed cell is shown to have guaranteed read-disturbance immunity, as during a read operation the net torque acting on the storage cell always acts to refresh the stored data in the cell. A simulation study is conducted to compare the merits of the proposed device against a conventional 1 Transistor, 1 MTJ (1T1MTJ) cell, as a well as a differential 2 Transistors, 2 MTJs (2T2MTJ) cell. Simulation results confirm that the proposed device offers disturbance-free read operation while still offering performance advantages over conventional cells.
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Modeling and Design of Spin Torque Transfer Magnetoresistive Random Access MemoryHuda, Safeen 15 November 2013 (has links)
This thesis presents the modeling and design of memory cells for Spin Torque Transfer Magnetoresistive Random Access Memory (STT-MRAM). The theory of operation of STT-MRAM cells is explored, and a model to predict the transient behaviour of STT-MRAM cells is presented. A novel three-terminal Magnetic Tunneling Junction (MTJ) and its associated cell structure is also presented. The proposed cell is shown to have guaranteed read-disturbance immunity, as during a read operation the net torque acting on the storage cell always acts to refresh the stored data in the cell. A simulation study is conducted to compare the merits of the proposed device against a conventional 1 Transistor, 1 MTJ (1T1MTJ) cell, as a well as a differential 2 Transistors, 2 MTJs (2T2MTJ) cell. Simulation results confirm that the proposed device offers disturbance-free read operation while still offering performance advantages over conventional cells.
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UML modeling for VHDL designs / Unified Modeling Language modeling for Very High Speed Integrated Circuit Hardware Description Language designsSprunger, Steven J. January 2008 (has links)
Unified Modeling Language (UML) allows software engineers to use a standard way of expressing a design approach at a high level. The benefits of system modeling are well accepted in the software development community. Modeling of Very High Speed Integrated Circuit Hardware Description Language (VHDL) designs, for synthesizing into hardware, is a common practice also. The research herein looks at system modeling of a design using UML, in which there are both software and hardware components. The idea is to explore modeling of the system with the ability to abstract whether the implementation of a particular function is realized in software or hardware. The designer can then model/evaluate a given system design approach and later allocate functions to software and hardware, as appropriate to meet constraints such as performance, cost, schedule. Since using UML for software is a standard approach, this research investigates the UML to hardware path via VHDL. / Department of Computer Science
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A parametrized CAD tool for VHDL model development with X Windows /Singh, Balraj, January 1990 (has links)
Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1990. / Vita. Abstract. Includes bibliographical references (leaves 52-54). Also available via the Internet.
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Assertion-checker synthesis for hardware verification, in-circuit debugging and on-line monitoringBoulé, Marc. January 1900 (has links)
Thesis (Ph.D.). / Written for the Dept. of Electrical and Computer Engineering. Title from title page of PDF (viewed 2008/05/09). Includes bibliographical references.
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Optimization techniques for distributed Verilog simulationLi, Lijun, January 1900 (has links)
Thesis (Ph.D.). / Written for the School of Computer Science. Title from title page of PDF (viewed 2008/02/12). Includes bibliographical references.
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