Orientador: Rodolfo Jardim de Azevedo / Dissertação (mestrado) - Universidade Estadual de Campinas, Instituto de Computação / Made available in DSpace on 2018-08-10T11:21:32Z (GMT). No. of bitstreams: 1 Sigrist_ThiagoMassariolli_M.pdf: 1159366 bytes, checksum: 1b73082be801a7391d4d5176c6e49207 (MD5) Previous issue date: 2007 / Resumo: O surgimento dos SoCs (Systems-on-Chip) levou ao desenvolvimento das metodologias de projeto baseadas em TLM (Transaction-Level Modelling), que oferecem diversas etapas de modelagem intermediárias entre a especificação pura e a descrição sintetizável RTL (Register Transfer Level ), tornando mais tratável o projeto de sistemas dessa complexidade. Levando-se em consideração que esses sistemas geralmente possuem microprocessadores como módulos principais, torna-se desejável o uso de linguagens de descrição de arquiteturas (ADLs ? Architecture Description Languages) como ArchC e suas ferramentas para que seja possível modelar esses processadores e gerar módulos simuladores para eles em uma fração do tempo tradicionalmente gasto com essa tarefa. Porém, ArchC, em sua penúltima versão, a 1.6, possui utilidade limitada para esse fim, pois os simuladores que é capaz de gerar são autocontidos, não sendo facilmente integráveis aos modelos TLM em nível de sistema como um todo. Este trabalho consiste em uma remodelagem da linguagem ArchC e sua ferramenta acsim de modo a acrescentar essa capacidade de integração aos simuladores funcionais interpretados que é capaz de gerar, dando assim origem à versão 2.0 de ArchC / Abstract: The advent of SoCs (Systems-on-Chip) lead to the development of project methodologies based on TLM (Transaction-Level Modelling), which consist of several modelling layers between pure specifications and synthesizable RTL (Register Transfer Level ) descriptions, making the complexity of such systems more manageable. Considering that those systems usually have microprocessors as main modules, it is desirable to use architecture description languages (ADLs) like ArchC and its toolkit to model those processors and generate simulator modules for them in a fraction of the time usually spent in that task. However, ArchC, in its previous version, 1.6, has limitations for that use, since the simulators it generates are self-contained, thus hard to integrate to TLM system-level models. This work consists in remodelling ArchC and its acsim tool, adding this ability of integration to its functional interpreted simulators, leading to version 2.0 of ArchC / Mestrado / Sistemas de Computação / Mestre em Ciência da Computação

In power distribution system planning, it is essential to understand the impacts that electric vehicles (EVs), and the non-linear, time-variant loading profiles associated with their charging units, may have on power distribution networks. This research presents a design methodology for the creation of both analytical and behavioral models for EV charging units within a VHDL-AMS simulation environment. Voltage and current data collected from Electric Avenue, located on the Portland State University campus, were used to create harmonic profiles of the EV charging units at the site. From these profiles, generalized models for both single-phase (Level 2) and three-phase (Level 3) EV chargers were created. Further, these models were validated within a larger system context utilizing the IEEE 13-bus distribution test feeder system. Results from the model's validation are presented for various charger and power system configurations. Finally, an online tool that was created for use by distribution system designers is presented. This tool can aid designers in assessing the impacts that EV chargers have on electrical assets, and assist with the appropriate selection of transformers, conductor ampacities, and protection equipment & settings.

Approved for public release, distribution is unlimited / This thesis outlines the development, programming, and testing a logical interface between a radar system, the AN/SPS-65(V)1, and a general-purpose reconfigurable computing platform, the SRC Computer, Inc. model, the SRC-6E. To confirm the proper operation of the interface and associated subcomponents, software was developed to perform basic radar signal processing. The interface, as proven by the signal processing results, accurately reflects radar imagery generated by the radar system when compared to maps of the surrounding area. The research accomplished here will allow follow on research to evaluate the potential benefits reconfigurable computing platforms offer for radar signal processing. / Captain, United States Marine Corps