Call number: LD2668 .T4 1986 B368 / Master of Science / Computing and Information Sciences

Hardware description languages provide digital system designers with a convenient, compact method for describing complex circuits. A Hardware Programming Language (AHPL) is a powerful description language based on the APL programming language. AHPL circuit descriptions can be unambiguously translated into a logic gate network using the HPCOM hardware compiler. The initial discussion section covers the conversion of the VAX version of HPCOM into a version which will run on MS-DOS microcomputers. The major portion of the research focuses on the development, use, and application of a graphics display tool for HPCOM-generated networks. The display package, SUBGRAPH, allows selected subgraphs of a network to be viewed and/or printed. The discussion of this research concludes with an extensive example of the complete circuit generation and graphics display sequence. The printed graphics examples feature cases of particular interest for test generation.

Le temps de mise sur le marché et les coûts d’implantation sont les deux critères principaux à prendre en compte dans l'automatisation du processus de conception de systèmes numériques. Les applications de traitement du signal utilisent majoritairement l'arithmétique virgule fixe en raison de leur coût d'implantation plus faible. Ainsi, une conversion en virgule fixe est nécessaire. Cette conversion est composée de deux parties correspondant à la détermination du nombre de bits pour la partie entière et pour la partie fractionnaire. Le raffinement d'un système en virgule fixe nécessite d'optimiser la largeur des données en vue de minimiser le coût d'implantation tout en évitant les débordements et un bruit de quantification excessif. Les applications dans les domaines du traitement d'image et du signal sont tolérantes aux erreurs si leur probabilité ou leur amplitude est suffisamment faible. De nombreux travaux de recherche se concentrent sur l'optimisation de la largeur de la partie fractionnaire sous contrainte de précision. La réduction du nombre de bits pour la partie fractionnaire conduit à une erreur d'amplitude faible par rapport à celle du signal. La théorie de la perturbation peut être utilisée pour propager ces erreurs à l'intérieur des systèmes à l'exception du cas des opérations un- smooth, comme les opérations de décision, pour lesquelles une erreur faible en entrée peut conduire à une erreur importante en sortie. De même, l'optimisation de la largeur de la partie entière peut réduire significativement le coût lorsque l'application est tolérante à une faible probabilité de débordement. Les débordements conduisent à une erreur d'amplitude élevée et leur occurrence doit donc être limitée. Pour l'optimisation des largeurs des données, le défi est d'évaluer efficacement l'effet des erreurs de débordement et de décision sur la métrique de qualité associée à l'application. L'amplitude élevée de l'erreur nécessite l'utilisation d'approches basées sur la simulation pour évaluer leurs effets sur la qualité. Dans cette thèse, nous visons à accélérer le processus d'évaluation de la métrique de qualité. Nous proposons un nouveau environnement logiciel utilisant des simulations sélectives pour accélérer la simulation des effets des débordements et des erreurs de décision. Cette approche peut être appliquée à toutes les applications de traitement du signal développées en langage C. Par rapport aux approches classiques basées sur la simulation en virgule fixe, où tous les échantillons d'entrée sont traités, l'approche proposée simule l'application uniquement en cas d'erreur. En effet, les dépassements et les erreurs de décision doivent être des événements rares pour maintenir la fonctionnalité du système. Par conséquent, la simulation sélective permet de réduire considérablement le temps requis pour évaluer les métriques de qualité des applications. De plus, nous avons travaillé sur l'optimisation de la largeur de la partie entière, qui peut diminuer considérablement le coût d'implantation lorsqu'une légère dégradation de la qualité de l'application est acceptable. Nous exploitons l'environnement logiciel proposé auparavant à travers un nouvel algorithme d'optimisation de la largeur des données. La combinaison de cet algorithme et de la technique de simulation sélective permet de réduire considérablement le temps d'optimisation. / Time-to-market and implementation cost are high-priority considerations in the automation of digital hardware design. Nowadays, digital signal processing applications use fixed-point architectures due to their advantages in terms of implementation cost. Thus, floating-point to fixed-point conversion is mandatory. The conversion process consists of two parts corresponding to the determination of the integer part word-length and the fractional part world-length. The refinement of fixed-point systems requires optimizing data word -length to prevent overflows and excessive quantization noises while minimizing implementation cost. Applications in image and signal processing domains are tolerant to errors if their probability or their amplitude is small enough. Numerous research works focus on optimizing the fractional part word-length under accuracy constraint. Reducing the number of bits for the fractional part word- length leads to a small error compared to the signal amplitude. Perturbation theory can be used to propagate these errors inside the systems except for unsmooth operations, like decision operations, for which a small error at the input can leads to a high error at the output. Likewise, optimizing the integer part word-length can significantly reduce the cost when the application is tolerant to a low probability of overflow. Overflows lead to errors with high amplitude and thus their occurrence must be limited. For the word-length optimization, the challenge is to evaluate efficiently the effect of overflow and unsmooth errors on the application quality metric. The high amplitude of the error requires using simulation based-approach to evaluate their effects on the quality. In this thesis, we aim at accelerating the process of quality metric evaluation. We propose a new framework using selective simulations to accelerate the simulation of overflow and un- smooth error effects. This approach can be applied on any C based digital signal processing applications. Compared to complete fixed -point simulation based approaches, where all the input samples are processed, the proposed approach simulates the application only when an error occurs. Indeed, overflows and unsmooth errors must be rare events to maintain the system functionality. Consequently, selective simulation allows reducing significantly the time required to evaluate the application quality metric. 1 Moreover, we focus on optimizing the integer part, which can significantly decrease the implementation cost when a slight degradation of the application quality is acceptable. Indeed, many applications are tolerant to overflows if the probability of overflow occurrence is low enough. Thus, we exploit the proposed framework in a new integer word-length optimization algorithm. The combination of the optimization algorithm and the selective simulation technique allows decreasing significantly the optimization time.

Thesis (M.S.E.C.E.)--Baylor University, 2008. / Includes bibliographical references (p. 322-323)

Techn. Hochsch., Diss. u.d.T.: Hoffmann, Andreas: A methodology for the efficient design of application-specific instruction-set processors using the machine description language LISA--Aachen, 2002.

Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, March 2005. / Thesis Advisor(s): Douglas J. Fouts. Includes bibliographical references (p. 61). Also available online.

Thesis (M.E.)--University of Canterbury, 2006. / Typescript (photocopy). "March 2006." Includes bibliographical references (p. 145-151). Also available via the World Wide Web.

Orientadores: Sandro Rigo, Rodolfo Jardim de Azevedo / Dissertação (mestrado) - Universidade Estadual de Campinas, Instituto de Computação / Made available in DSpace on 2018-08-19T17:27:58Z (GMT). No. of bitstreams: 1 Garcia_MaxiwellSalvador_M.pdf: 2001408 bytes, checksum: 18a0b7e502a8676d32857b27374a5d77 (MD5) Previous issue date: 2011 / Resumo: O simulador é uma das ferramentas mais importantes para o desenvolvimento de uma nova arquitetura computacional. Entre as vantagens que ele apresenta destacam-se a flexibilidade e o baixo custo. Os primeiros simuladores eram criados manualmente, uma prática muito propensa a erros. Atualmente, Linguagens de Descrição de Arquiteturas (ADLs) facilitam a geração dessas ferramentas. O foco deste trabalho é a pesquisa em técnicas de simulação rápida utilizando a ADL ArchC. Partindo do estado da arte nesta área, a simulação compilada, conseguiu-se melhorar ainda mais o desempenho dos simuladores de conjunto de instruções. Duas abordagens compilada foram usadas. A primeira é uma abordagem estática, que analisa e decodifica o binário previamente e especializa o simulador para aquela aplicação, deixando a simulação com um alto desempenho. As simulações ficaram apenas 5 vezes mais lentas, na média, que execuções nativas em máquina Intel, com desempenho atingindo 900 milhões de instruções por segundo. A segunda abordagem é a dinâmica, que não exige o conhecimento prévio da aplicação, evitando a sobrecarga inicial de se especializar o simulador. Com essa abordagem é possível, também, simular aplicativos que sofrem modificações em seu próprio código, como boot-loader e sistemas operacionais. A decodificação e compilação do aplicativo são feitas em tempo de execução, fazendo uso da infraestrutura LLVM. O desempenho de simulação só não superou o estático, alcançando uma média de 140 milhões de instruções por segundo. Considerando-se a sobrecarga de geração do simulador compilado estático, a abordagem dinâmica torna-se mais rápida, mostrando-se uma excelente alternativa ao projetista que não tem o interesse em ficar simulando repetidas vezes a mesma aplicação / Abstract: The simulator is one of the most important tools to design a new computer architecture. It has many advantages, the most important are exibility and low cost. The _rst simulators were written from scratch, which was an error-prone practice. Nowadays, Architecture Description Languages (ADLs) simplify the generation of these tools. This work focus on the research of new fast simulation techniques using the ArchC ADL. Beginning from the state-of-art in this area, the compiled simulation, is was possible to speed-up the instruction set simulation performance even higher. Two approaches have been used. The _rst is static compiled simulation, which analyzes and decodes the binary, and specializes the simulator for that application, improving the simulation and reaching high performance. The simulations were only 5 times slower, on average, if compared to native execution on an Intel machine, reaching 900 million instructions per second. The second approach is a dynamic compiled simulation, which requires no knowledge about the application, avoiding the overhead of specializing the simulator. With this approach it is possible to simulate sef-modifying code, such as in boot-loaders and operating systems. The application is decoded and compiled at runtime, using the LLVM framework. The simulation performance reaches an average of 140 million instructions per second, not overcoming the static approach. However, if you consider the overhead of generating the static compiled simulator, the dynamic approach becomes better, being an excellent alternative to the designer who has no interest in repeating simulations for the same application / Mestrado / Ciência da Computação / Mestre em Ciência da Computação

This thesis is one of the first to introduce a systematic and general Source Language Analysis System (called SLA) for a high -level synthesis system.

Thesis (M.Eng.)--Memorial University of Newfoundland, 1999. / Bibliography: leaves 100-102.