Due to the rapidly increasing complexity in hardware designs and competitive time to market trends in the industry, there is an inherent need to move designs to a higher level of abstraction. Behavioral Synthesis is the process of automatically compiling such Electronic System Level (ESL) designs written in high-level languages such as C, C++ or SystemC into Register-Transfer Level (RTL) implementation in hardware description languages such as Verilog or VHDL. However, the adoption of this flow is dependent on designers' faith in the correctness of behavioral synthesis tools. Loop pipelining is a critical transformation employed in behavioral synthesis process, and ubiquitous in commercial and academic behavioral synthesis tools. It improves the throughput and reduces the latency of the synthesized hardware. It is complex and error-prone, and a small bug can result in faulty hardware with expensive ramifications. Therefore, it is critical to certify the loop pipelining transformation so that designers can trust the behaviorally synthesized pipelined designs. Certifying a loop pipelining transformation is however, a major research challenge because there is a huge semantic gap between the input sequential design and the output pipelined implementation, making it infeasible to verify their equivalence with automated sequential equivalence checking (SEC) techniques. Complex loop pipelining transformations can be certified by a combination of theorem proving and SEC: (1) creating a certified pipelining algorithm which generates a reference pipeline model by exploiting pipeline generation information from the synthesis flow (e.g. the iteration interval of a generated pipeline) and (2) conduct SEC between the synthesized pipeline and this reference model. However, a key and arguably, the most complex component of this approach is the development of a formal, mechanically verifiable loop pipelining algorithm. We show how to systematically construct such an algorithm, and carry out its verification using the ACL2 theorem prover. We propose a framework of certified pipelining primitives which are essential for designing pipelining algorithms. Using our framework, we build a certified loop pipelining algorithm. We also propose a key invariant in certifying this algorithm, which links sequential loops with their pipelined counterparts. This is unlike other invariants that have been used in proofs of microprocessor pipelines so far. This dissertation provides a framework for creating certified pipelining algorithms utilizing a mechanical theorem prover. Using this framework, we have developed a certified loop pipelining algorithm. This certified algorithm is essential in the overall approach to certify behaviorally synthesized pipelined designs. We demonstrate the scalability and robustness of our algorithm on several ESL designs across various domains.

The aggressive evolution of the semiconductor industry smaller process geometries, higher densities, and greater chip complexity has provided design engineers the means to create complex, high-performance System-on-a-Chip (SoC) designs. Such SoC designs typically have more than one processor and huge (tens of Mega Bytes) amount of memory, all on the same chip. Dealing with the global on-chip memory allocation/deallocation in a dynamic yet deterministic way is an important issue for upcoming billion transistor multiprocessor SoC designs. To achieve this, we propose a memory management hierarchy we call Two-Level Memory Management. To implement this memory management scheme which presents a shift in the way designers look at on-chip dynamic memory allocation we present the System-on-a-Chip Dynamic Memory Management Unit (SoCDMMU) for allocation of the global on-chip memory, which we refer to as Level Two memory management (Level One is the management of memory allocated to a particular on-chip Processing Element, e.g., an operating systems management of memory allocated to a particular processor). In this way, processing elements (heterogeneous or non-heterogeneous hardware or software) in an SoC can request and be granted portions of the global memory in a fast and deterministic time. A new tool is introduced to generate a custom optimized version of the SoCDMMU hardware. Also, a real-time operating system is modified support the new proposed SoCDMMU. We show an example where shared memory multiprocessor SoC that employs the Two-Level Memory Management and utilizes the SoCDMMU has an overall average speedup in application transition time as well as normal execution time.

People are increasingly concerned about online privacy and how computers collect, process, share, and store their personal information. Such concerns are understandable given the growing number of privacy invasions and the pervasiveness of information capture and sharing between IT systems. This situation has led to an increasingly regulated environment, limiting what systems may do, and what safeguards they must offer users. Privacy is an especially important concern in the fields of computer supported collaborative work (CSCW), Ubiquitous Computing, and e-commerce, where the nature of the applications often requires some information collection and sharing. In order to minimize risks to users it is essential to identify privacy problems early in the design process. Several methods and frameworks for accomplishing this have been proposed in the last decades. These frameworks, though based on hard-earned experience and great insight, have not seen widespread adoption despite the high level of interest in this topic. Part of the reason for this is likely the lack of evaluation and study of these frameworks. In our research we examine the key design and analysis frameworks and their elements, and compare these to the kinds of problems users face and are concerned with in terms of privacy. Based on this analysis of the relative strengths and weaknesses of existing design frameworks we derive a new design framework; STRAP (STRuctured Analysis of Privacy). In STRAP we combine light-weight goal-oriented analysis with heuristics to provide a simple yet effective design framework. We validate our analysis by demonstrating in a series of design experiments that STRAP is more efficient and effective than any one of the existing design frameworks, and provide quantitative and qualitative evidence of the value of using such frameworks as part of the design process.

Thesis (M. Tech.: Information Technology)-Dept. of Information Technology, Durban Institute of Technology, 2005 xiv, 170, [20] leaves / This study examines the efficiency, ease of use and ease of understanding of user interface designs implemented in current e-commerce websites. Four South African based e-commerce websites formed the test cases of this study. Selection of the test cases was based on the results and conclusions of previous surveys conducted by an independent research institution. The outcome of that survey identified the most popular e-commerce websites among South African internet users.

Thesis (PhD) - Swinburne University of Technology, 2006. / [Submitted for the degree of Doctor of Philosophy, Swinburne University of Technology - 2006]. Typescript. Includes bibliographical references (p. 218-231).

Thesis MTech(Electrical Engineering)--Cape Technikon, Cape Town, 1996 / The development of the 8051 Evaluation and Training Board was in response to fulfill a need to have a training board available for students at the start of a micro-controller course. This board must be used to get hands-on experience in the internal architecture, programming and operation of the controller through the testing of sample programs and exercises. It can act as an example of a practical micro-controller application board, and also as part of, or as an aid in the design and application of own projects. The board had to be cheap enough so that each student can be issued with a personal board for the duration of the course. It had to be adequately selfsufficient to be portable and to operate independent of a host PC. In addition, it had to contain adequate "intelligence" to guide the student in the use of the board: have a quick re-programming turn-around cycle; and it must be possible to use the board for user program testing and debugging. After drawing up an initial set of objectives and investigating the economic viability of similar systems in industry, an outline of the required design was made. This included the selection of suitable communication between the onboard Operating System and a user; the easiest way to load user programs into the board memory; and methods to test and debug this program. All the normal support circuitry required by a micro-controller to accommodate a minimum system for operation was included into a single Field Programmable Gate Array. The execution of the project was therefore divided into three distinct sections, the hardware, the firmware (Programmable Array configuration) and the software. In the design, the harmony between these sections had to be consolidated to yield a successful final product. The simplicity and ergonomics of the operation and application from a user's point of view, had to be accentuated and kept in mind throughout. In a design of the complexity such as this, careful planning and the investigation of various methods of approach were essential. The use of many computer-aided design and other relevant computer packages was incorporated. Interaction between the user and the Operating System on the board was done through a standard 16-character by 1-line LCD Display Module and a 32-key keyboard. The main feature of the Operating System was to enable the inspection and editing of all the memory locations on the micro-processor.

The use of embedded Internet systems is growing rapidly in the manufacturing sector. These systems allow the monitoring and controlling of plant machinery and manufactured items from a remote location via a standard Web interface. In a manufacturing environment, it is inevitable that long running processes will require support for dynamic reconfiguration because, for example, machines may fail, services may be moved or withdrawn and user requirements may change. In such an environment it is essential that the operation and architecture of such processes can be modified to reflect such changes. This research project will present methods and ideas for establishing a reconfigurable remote system by using standard 8-bit microcontrollers and reconfigurable hardware. It will allow a manufacturing process to be modified and changed within minutes without even having to be physically present at the location where the process is running.

Design guidelines are used in interaction design (IxD) for physical design and for evaluating the usability of designs and interactive products. Guidelines are widely used for physical design and evaluation, but have a number of problems. IxD patterns have been proposed as an alternative to guidelines, as they are claimed to have several advantages over guidelines. A small number of empirical studies provide evidence that patterns are beneficial when used in IxD. Additional research on the usefulness of IxD patterns is required. The primary research question investigated in this thesis was thus: How useful are IxD patterns as physical design and evaluation aids in IxD, as compared to design guidelines? The role of guidelines and patterns as design and evaluation aids in IxD was investigated and a comparison of guidelines and patterns, based on a set of guideline and pattern properties, was conducted. The concept of pattern and guideline usefulness was explored and a research agenda for guidelines and patterns was identified, together with a set of research questions for an empirical study. The empirical study of the use of patterns for evaluation, redesign and new design, as compared to guidelines, was conducted at the Nelson Mandela Metropolitan University in 2004. The participants were a purposive sample of post-graduate Computing students, who were regarded as novice interaction designers. Two equivalent groups were formed, one that used patterns and one that used guidelines. Patterns were found to be as useful as guidelines when used as evaluation aids. Guidelines and patterns were identified as effective tools for identifying and explaining usability issues and design features. Best-effort matched sets of guidelines and patterns produced substantially different result sets when used to identify issues and features, with fairly low overlap. A substantial evaluator effect was observed for the use of guidelines and patterns for evaluation, and the results obtained were similar to those obtained by Molich et al. in their Comparative Usability Evaluation (CUE) studies. There was no statistically significant difference between the effectiveness of guidelines and patterns for evaluation. There was also no statistically significant difference between the perceived efficiency, effectiveness and satisfaction in use of guidelines and patterns for evaluation. Guidelines and patterns were found to be used in similar ways for evaluation. Patterns were found to be more effective than guidelines for redesign. Patterns were found to be as useful as guidelines when used for new design. There was no statistically significant difference between the effectiveness of guidelines and patterns for new design. There was also no statistically significant difference between the perceived efficiency, effectiveness and satisfaction in use of guidelines and patterns for redesign and new design. Guidelines and patterns were found to be used in similar ways for design. There was no statistically significant difference between the perceived usefulness of the format, content, ease of learning, and usefulness as personal and shared design languages, of guidelines and patterns. Both participant groups were equally agreeable to using guidelines and patterns in the future. The perceived usefulness of pattern collections was found to depend on the usability of the collection interface and the content quality of the patterns. The results of the empirical study thus provided empirical evidence that patterns were as useful as guidelines for evaluation and new design, and were perceived as positively as guidelines were. Patterns were found to be superior to guidelines for redesign. Patterns can therefore be used with a measure of confidence as early stage design aids for physical design and evaluation in the future. In addition to these findings, a number of opportunities for further research were identified.

Mobile devices today frequently serve as platforms for the visualisation of map-based data. Despite the obvious advantages, mobile map-based visualisation (MMV) systems are often difficult to design and use. Limited screen space, resource constraints and awkward interaction mechanisms are among the many problems with which designers and users have to contend. Adaptive user interfaces (AUIs), which adapt to the individual user, represent a possible means of addressing the problems of MMV. Adaptive MMV systems are, however, generally designed in an ad-hoc fashion, making the benefits achieved difficult to replicate. In addition, existing models for adaptive MMV systems are either conceptual in nature or only address a subset of the possible input variables and adaptation effects. The primary objective of this research was to develop and evaluate an adaptive MMV system using a model-based approach. The Proteus Model was proposed to support the design of MMV systems which adapt in terms of information, visualisation and user interface in response to the user‟s behaviour, tasks and context. The Proteus Model describes the architectural, interface, data and algorithm design of an adaptive MMV system. A prototype adaptive MMV system, called MediaMaps, was designed and implemented based on the Proteus Model. MediaMaps allows users to capture, location-tag, organise and visualise multimedia on their mobile phones. Information adaptation is performed through the use of an algorithm to assist users in sorting media items into collections based on time and location. Visualisation adaptation is performed by adapting various parameters of the map-based visualisations according to user preferences. Interface adaptation is performed through the use of adaptive lists. An international field study of MediaMaps was conducted in which participants were required to use MediaMaps on their personal mobile phones for a period of three weeks. The results of the field study showed that high levels of accuracy were achieved by both the information and interface adaptations. High levels of user satisfaction were reported, with participants rating all three forms of adaptation as highly useful. The successful implementation of MediaMaps provides practical evidence that the model-based design of adaptive MMV systems is feasible. The positive results of the field study clearly show that the adaptations implemented were highly accurate and that participants found these adaptations to be useful, usable and easy to understand. This research thus provides empirical evidence that the use of AUIs can provide significant benefits for the visualisation of map-based information on mobile devices.

In contrast to a traditional setting where users express queries against the database schema, we assert that the semantics of data can often be understood by viewing the data in the context of the user interface (UI) of the software tool used to enter the data. That is, we believe that users will understand the data in a database by seeing the labels, dropdown menus, tool tips, help text, control contents, and juxtaposition or arrangement of controls that are built in to the user interface. Our goal is to allow domain experts with little technical skill to understand and query data. In this dissertation, we present our GUi As View (Guava) framework and describe how we use forms-based UIs to generate a conceptual model that represents the information in the user interface. We then describe how we generate a query interface from the conceptual model. We characterize the resulting query language using a subset of relational algebra. Since most application developers want to craft a physical database to meet desired performance needs independent of the schema used by the user interface, we subsequently present a general-purpose schema mapping tool called a channel that can be configured by instantiating a sequence of discrete transformations. Each transformation is an encapsulation of a physical design decision or business logic process. The channel, once configured, automatically transforms queries from our query interface into queries that address the underlying physical database, similar to a view. The channel also transforms data updates, schema updates, and constraint definitions posed against the channel’s input schema into equivalent forms against the physical schema. We present formal definitions of each transformation and properties that must be true of transformations, and prove that our definitions respect the properties.