The underlying goal of SUPERvisory Methodology And Notation (SUPERMAN) is to enhance productive operation of human-computer system developers by providing easy-to-use concepts and automated tools for developing high-quality (e.g., human-engineered, cost-effective, easy-to-maintain) target systems. The supervisory concept of the methodology integrates functions of many modeling techniques, and allows complete representation of the designer's conceptualization of a system's operation. The methodology views humans as functional elements of a system in addition to computer elements. Parts of software which implement human-computer interaction are separated from the rest of software. A single, unified system representation is used throughout a system lifecycle. The concepts of the methodology are notationally built into a graphical programming language. The use of this language in developing a system leads to a natural and orderly application of the methodology. / Ph. D. / incomplete_metadata

A common concern for people using computer databases is becoming "lost" within the complex hierarchy of entries. Most direct manipulation interface design guidelines suggest designers should include a feature for “undoing” user inputs (Smith and Mosier, 1986). In the case of a database, undo translates to backtracking support. The first purpose of this research was to confirm that computer-supported backtracking tools reduce navigation time over manual backtracking. The second purpose was to compare navigation times among a subset of backtracking tools. The third purpose was to determine if users prefer to use one or more backtracking tools significantly more than others. Four backtracking tools were developed by crossing two factors: History (history list vs no history list) and Level (component vs entry). History list indicates the user may view a chronological listing of nodes that have been viewed and directly select a destination node. No history list means the user must backtrack through each visited node with no shortcuts. Component indicates the backtracking tools operate only at the lowest level, or smallest definable node, of the tree-like database structure. Entry means that backtracking occurs at the higher parent node. Thus, multiple components make up an entry . In addition to the four computer backtracking tools, overall navigating and manual backtracking was done using a hierarchical Table of Contents. The tools were evaluated in an experimental, hierarchical, direct-manipulation database. Trials were conducted in the form of a multiple-choice information retrieval task. The independent variables included the backtracking tool (four-computer supported, one-manual) and the backtrack Task Length. The dependent measures included navigation time, the frequency with which the computer tool was used over manual backtracking (Table of Contents), and questionnaire responses. The results of this study provided some of the first solid support for the many guidelines that have been written recommending user recovery, or undo support. Backtracking with any of the four computer-supported tools resulted in a significantly smaller navigation time than manual backtracking using the Table of Contents. Subjects using either of the entry tools had consistent backtracking times across trials regardless of backtrack task length. When provided with a history list, subjects in the entry condition had significantly smaller navigation times than subjects in the component condition. Users did not show any differences between computer tools in rated efficiency, ease of use, or objective preference measures. / Master of Science

A systems engineering life-cycle approach is used to design the Facilities Automated Scheduling Tool (FAST) for the Facilities Branch of the ABC Company. The emphasis of the proposed design is the human factors criteria that are used to optimize the human-computer interface (HCI). The need identified by the Facilities Branch is that the current manual project tracking system takes three weeks to gather the information required to initiate a request for change (RFC). Paperwork is cumbersome, data files are difficult to locate, and the Facilities Specialists are inundated with fragmented reports filed away in cabinets that are taking up what little free space the office has left. Therefore, the requirements for the system are established, options considered, and a recommended design is achieved which will reduce the number of file cabinets by 80%, enable a project to be input into the system in fifteen minutes, and reduce the number of data input specialists from three to one, saving the company time and money. FAST is essential to the Facilities Branch for optimal efficiency and cost-effective performance. Furthermore, many different operators need the system to track their specific projects. Most of these Facilities Specialists are not "regular" computer users, therefore, user-friendliness is of critical importance. Analyzing human factors options and presenting trade-offs is of utmost importance to ensure FAST will be used properly. If the user becomes frustrated with the system, the tool will no longer be useful to the operator or the Facilities Branch. Both the hardware and software configurations of FAST are examined for user-friendliness and efficiency. The ABC Company has a service contract with IBM, where all the hardware equipment is bought. Therefore, an IBM platform is assumed for FAST. However, various screen designs and workstation arrangements are examined in order to produce a safe. comfortable, reliable, and efficient system that will save the ABC Company time and money. / Master of Science

With a focus on dynamics and control, an aquatic quadcopter with optical wireless communications is modeled, designed, constructed, and tested. Optical transmitter and receiver circuitry is designed and discussed. By utilization of the small angle assumption, the nonlinear dynamics of quadcopter movement are linearized around an equilibrium state of zero motion. The set of equations are then tentatively employed beyond limit of the small angle assumption, as this work represents an initial explorative study. Specific constraints are enforced on the thrust output of all four rotors to reduce the multiple-input multiple-output quadcopter dynamics to a set of single-input single-output systems. Root locus and step response plots are used to analyze the roll and pitch rotations of the quadcopter. Ultimately a proportional integral derivative based control system is designed to control the pitch and roll. The vehicle’s yaw rate is similarly studied to develop a proportional controller. The prototype is then implemented via an I2C network of Arduino microcontrollers and supporting hardware. / Includes bibliography. / Thesis (M.S.)--Florida Atlantic University, 2016. / FAU Electronic Theses and Dissertations Collection

Ping-Ki Tsang. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2000. / Includes bibliographical references (leaves 87-95). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgments --- p.iii / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivation and Aims --- p.1 / Chapter 1.2 --- Contributions --- p.3 / Chapter 1.3 --- Overview of the Thesis --- p.4 / Chapter 2 --- Asynchronous Logic g --- p.6 / Chapter 2.1 --- Motivation --- p.6 / Chapter 2.2 --- Timing Models --- p.9 / Chapter 2.2.1 --- Fundamental-Mode Model --- p.9 / Chapter 2.2.2 --- Delay-Insensitive Model --- p.10 / Chapter 2.2.3 --- QDI and Speed-Independent Models --- p.11 / Chapter 2.3 --- Asynchronous Signalling Protocols --- p.12 / Chapter 2.3.1 --- 2-phase Handshaking Protocol --- p.12 / Chapter 2.3.2 --- 4-phase Handshaking Protocol --- p.13 / Chapter 2.4 --- Data Representations --- p.14 / Chapter 2.4.1 --- Dual Rail Coded Data --- p.15 / Chapter 2.4.2 --- Bundled Data --- p.15 / Chapter 2.5 --- Previous Asynchronous Processors --- p.16 / Chapter 2.6 --- Summary --- p.20 / Chapter 3 --- The MSL16 Architecture --- p.21 / Chapter 3.1 --- RISC Machines --- p.21 / Chapter 3.2 --- Stack Machines --- p.23 / Chapter 3.3 --- Forth and its Applications --- p.24 / Chapter 3.4 --- MSL16 --- p.26 / Chapter 3.4.1 --- Architecture --- p.28 / Chapter 3.4.2 --- Instruction Set --- p.30 / Chapter 3.4.3 --- The Datapath --- p.32 / Chapter 3.4.4 --- Interrupts and Exceptions --- p.33 / Chapter 3.4.5 --- Implementing Forth primitives --- p.34 / Chapter 3.4.6 --- Code Density Estimation --- p.34 / Chapter 3.5 --- Summary --- p.35 / Chapter 4 --- Design Methodology --- p.37 / Chapter 4.1 --- Basic Notation --- p.38 / Chapter 4.2 --- Specification of MSL16A --- p.39 / Chapter 4.3 --- Decomposition into Concurrent Processes --- p.41 / Chapter 4.4 --- Separation of Control and Datapath --- p.45 / Chapter 4.5 --- Handshaking Expansion --- p.45 / Chapter 4.5.1 --- 4-Phase Handshaking Protocol --- p.46 / Chapter 4.6 --- Production-rule Expansion --- p.47 / Chapter 4.7 --- Summary --- p.48 / Chapter 5 --- Implementation --- p.49 / Chapter 5.1 --- C-element --- p.49 / Chapter 5.2 --- Mutual Exclusion Elements --- p.51 / Chapter 5.3 --- Caltech Asynchronous Synthesis Tools --- p.53 / Chapter 5.4 --- Stack Design --- p.54 / Chapter 5.4.1 --- Eager Stack Control --- p.55 / Chapter 5.4.2 --- Lazy Stack Control --- p.56 / Chapter 5.4.3 --- Eager/Lazy Stack Datapath --- p.53 / Chapter 5.4.4 --- Pointer Stack Control --- p.61 / Chapter 5.4.5 --- Pointer Stack Datapath --- p.62 / Chapter 5.5 --- ALU Design --- p.62 / Chapter 5.5.1 --- The Addition Operation --- p.63 / Chapter 5.5.2 --- Zero-Checker --- p.64 / Chapter 5.6 --- Memory Interface and Tri-state Buffers --- p.64 / Chapter 5.7 --- MSL16A --- p.65 / Chapter 5.8 --- Summary --- p.66 / Chapter 6 --- Results --- p.67 / Chapter 6.1 --- FPGA based implementation of MSL16 --- p.67 / Chapter 6.2 --- MSL16A --- p.69 / Chapter 6.2.1 --- A Comparison of 3 Stack Designs --- p.69 / Chapter 6.2.2 --- Evaluation of the ALU --- p.73 / Chapter 6.2.3 --- Evaluation of MSL16A --- p.74 / Chapter 6.3 --- Summary --- p.81 / Chapter 7 --- Conclusions --- p.83 / Chapter 7.1 --- Future Work --- p.85 / Bibliography --- p.87 / Publications --- p.95

We present a body of work aimed at understanding and improving the security posture of embedded devices. We present results from several large-scale studies that measured the quantity and distribution of exploitable vulnerabilities within embedded devices in the world. We propose two host-based software defense techniques, Symbiote and Autotomic Binary Structure Randomization, that can be practically deployed to a wide spectrum of embedded devices in use today. These defenses are designed to overcome major challenges of securing legacy embedded devices. To be specific, our proposed algorithms are software- based solutions that operate at the firmware binary level. They do not require source-code, are agnostic to the operating-system environment of the devices they protect, and can work on all major ISAs like MIPS, ARM, PowerPC and X86. More importantly, our proposed defenses are capable of augmenting the functionality of embedded devices with a plethora of host-based defenses like dynamic firmware integrity attestation, binary structure randomization of code and data, and anomaly-based malcode detection. Furthermore, we demonstrate the safety and efficacy of the proposed defenses by applying them to a wide range of real- time embedded devices like enterprise networking equipment, telecommunication appliances and other commercial devices like network-based printers and IP phones. Lastly, we present a survey of promising directions for future research in the area of embedded security.

As today's real-time embedded systems grow increasingly ubiquitous, rising complexity ensues as more and more functionalities are integrated. Market dynamics and competitiveness further constrict the technology-to-market time requirement, consequently pushing it to the very forefront of consideration during the development process. Traditional system development approaches could no longer efficiently cope with such formidable demands, and a paradigm shift has been perceived by many as a mandate. This thesis presents a novel platform-centric SoC design method that relies on a platform-based design to expedite the overall development process. The proposed approach offers a new perspective towards the complex systems design paradigm, and can attain the desired paradigm shift through extensive reuse and flexibility. It offers a unified communication means for all sectors involved in the development process: Semiconductor vendors can use it to publish their platform specifications; Tool vendors can use it to develop and/or enhance their tools; System developers can use it to efficiently develop the system. Key technologies are also identified, namely the Extensible Markup Language (XML) and the Unified Modeling Language (UML), that realize the proposed approach. This thesis extends XML to attain a standard means for modeling, and processing a large amount of reusable platform-related data. Additionally, it employs UML's own extension mechanism to derive a UML dialect that can be used to model real-time systems and characteristics. This UML dialect, i.e. the UML profile for Codesign Modeling Framework (UML-CMF), remains compliant to the UML standard. A sub-profile within the UML profile for Codesign Modeling Framework is also developed so as to furnish a means for efficient modeling of platforms, and that can be seamlessly integrated with other real-time modeling capabilities offered by the UML-CMF. Such an effort yields a robust UML-compliant language that is suitable for a general platform-based modeling and design. A practical use of the proposed approach is demonstrated through a powerful case study that applies the approach to develop a digital camera system. The results are comparatively presented against the SpecC approach in terms of cost metrics based on the COCOMO II model.

Thesis (MBA)--Stellenbosch University, 2003. / ENGLISH ABSTRACT: The effective application of the requirements of customer interface design is critical for the success of business-to-consumer electronic commerce ventures. The challenging environment experienced by South African-based business-to-consumer electronic commerce compounds the importance of offering Web sites with high usability and a conventional shopping experience. The first main objective of this study is to determine the requirements of customer interface design in business-to-consumer electronic commerce and is achieved through the review of the relevant literature. The second main objective is to measure the application of customer interface design within South African business-to-consumer electronic commerce. A thematic model (or framework) that represents the thirteen main requirements is developed. The model identifies the themes as transmission speed, page layout and structure, navigation, writing style, multimedia, customer support, customisation and personalisation, community, information, perceptions, trust and security, commerce, and the absence of errors. The model is used to subjectively measure the effective application of customer interface design in a test group of fifty South African-based Web sites. The third main objective is to present the results. Requirements that are effectively applied by most of the Web sites include the themes of transmission speed, page layout and structure, writing style, multimedia, trust and security and the absence of errors. The themes of navigation, customisation and personalisation, information, perceptions and commerce are evident, but applied less effectively. Although some sites do provide the theme of customer support, the overall result shows that it is generally not effectively applied. Community is the least effectively applied of all the requirements presented in the thematic model. Possible reasons for the results are offered, but further research is necessary to determine the underlying reasons for lack of the community theme. The relevance and the value of the study lies in the conceptualisation of customer interface design in South African business-to-consumer electronic commerce and the foundation presented for future research. / AFRIKAANSE OPSOMMING: Die effektiewe toepassing van klant-koppelvlak ontwerp vereistes is noodsaaklik om die sukses van besigheid-tot-verbruiker elektroniese handel ondememings te verseker. Die uitdagende omgewing vir besigheid-tot-verbruiker elektroniese handel in Suid-Afrika beklemtoon die belangrikheid van webtuistes om gebruikersvriendelik te wees en 'n konvensionele inkopie-ervaring te bied. Die studieprojek se eerste doelwit is om die vereistes van klant-koppelvlak ontwerp in besigheid-tot-verbruiker elektroniese handel te bepaal. Hierdie doelwit word bereik deur 'n oorsig van die relevante literatuur. Die tweede doelwit is om die toepassing van klant-koppelvlak ontwerp in SuidAfrikaanse besigheid-tot-verbruiker elektroniese handel te meet. 'n Tematiese model, wat dertien hoofvereistes saamvat, is ontwerp om meting te fasiliteer. Die model identifiseer die temas van deursendingspoed, bladuitleg en -struktuur, navigasie, skryfstyl, multimedia, klantediens, aanpassing en verpersoonliking, gemeenskap, informasie, persepsies, vertroue en sekerheid, handel, en foutloosheid. Die model is gebruik om die effektiewe toepassing van klant-koppelvlak ontwerp ten opsigte van vyftig Suid-Afrikaanse webtuistes te meet. Die derde doelwit is om die resultate te analiseer en te interpreteer. Vereistes wat meestal effektief toegepas word, is die temas van deursendingspoed, bladuitleg en - struktuur, skryfstyl, multimedia, vertroue en sekerheid, en foutloosheid. Die temas van navigasie, aanpassing en verpersoonliking, informasie, persepsies en handel is teenwoordig, maar minder effektief toegepas. Alhoewel sommige webtuistes die tema van klantediens bied, dui die verwerkte resultate daarop dat dit in die algemeen nie effektief toegepas word nie. Van al die vereistes, soos in die tematiese model saamgevat, is gemeenskap die swakste toegepas. Moontlike redes vir die resultaat word aangebied, maar verdere navorsing is nodig om die onderliggende redes vas te stel. Die toepaslikheid en waarde van die navorsing is gelee in die konseptualisering van klant-koppelvlak ontwerp in die Suid-Afrikaanse besigheid-tot-verbruiker elektroniese handel, sowel as die grondslag wat dit vir verdere navorsing bied.

In this dissertation, we implement efficient lock-based synchronization by a novel, high performance, simple and scalable hardware technique and associated software for a target shared-memory multiprocessor System-on-a-Chip (SoC). The custom hardware part of our solution is provided in the form of an intellectual property (IP) hardware unit which we call the SoC Lock Cache (SoCLC). SoCLC provides effective lock hand-off by reducing on-chip memory traffic and improving performance in terms of lock latency, lock delay and bandwidth consumption. The proposed solution is independent from the memory hierarchy, cache protocol and the processor architectures used in the SoC, which enables easily applicable implementations of the SoCLC (e.g., as a reconfigurable or partially/fully custom logic), and which distinguishes SoCLC from previous approaches. Furthermore, the SoCLC mechanism has been extended to support priority inheritance with an immediate priority ceiling protocol (IPCP) implemented in hardware, which enhances the hard real-time performance of the system. Our experimental results in a four-processor SoC indicate that SoCLC can achieve up to 37% overall speedup over spin-lock and up to 48% overall speedup over MCS for a microbenchmark with false sharing. The priority inheritance implemented as part of the SoCLC hardware, on the other hand, achieves 1.43X speedup in overall execution time of a robot application when compared to the priority inheritance implementation under the Atalanta real-time operating system. Furthermore, it has been shown that with the IPCP mechanism integrated into the SoCLC, all of the tasks of the robot application could meet their deadlines (e.g., a high priority task with 250us worst case response time could complete its execution in 93us with SoCLC, however the same task missed its deadline by completing its execution in 283us without SoCLC). Therefore, with IPCP support, our solution can provide better real-time guarantees for real-time systems. To automate SoCLC design, we have also developed an SoCLC-generator tool, PARLAK, that generates user specified configurations of a custom SoCLC. We used PARLAK to generate SoCLCs from a version for two processors with 32 lock variables occupying 2,520 gates up to a version for fourteen processors with 256 lock variables occupying 78,240 gates.

Current electrical systems are faced with the limitation in performance by the electrical interconnect technology determining overall processing speed. In addition, the electrical interconnects containing many long distance interconnects require high power to drive. One of the best ways to overcome these bottlenecks is through the use of optical interconnect to limit interconnect latency and power. This research explores new computer-aided design algorithms for developing optoelectronic systems. These algorithms focus on place and route problems using optical interconnections covering system-on-a-chip design as well as system-on-a-package design. In order to design optoelectronic systems, optical interconnection models are developed at first. The CAD algorithms include optical interconnection models and solve place and route problems for optoelectronic systems. The MCNC and GSRC benchmark circuits are used to evaluate these algorithms.